library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all; 


entity SDModulator is
	
													-- Ports Anlegen--
	
	port ( 	dIn: in unsigned (9 downto 0);   
			clk: in std_logic;
			dOut: out std_logic );
			
end SDModulator;


architecture Modulator of SDModulator is
	
													-- Hilfssignale anlegen--

signal dIn_temp: 			unsigned  (10 downto 0);
signal dIn_neu: 			unsigned  (10 downto 0);
signal dIn_alt:				unsigned  (10 downto 0);
signal dOutm:	 			unsigned (9 downto 0);
signal Q:					unsigned  (10 downto 0);
signal dOut_read:			signed;
signal dIn_un:				unsigned  (9 downto 0);

begin 
											-- Signale mit '0' initalisieren -- 
	
	doutm <= (others => '0');
	din_alt <= (others => '0');

	Differenz: process (dIn, dOutm)					-- Differenzbildung am 1. Knoten --
	begin
		
		dIn_temp <= dIn - dOutm & '0';
		
	
	end process Differenz;
	

	Addiere: process (dIn_temp, dIn_alt)						-- Addition am 2. Knoten --
	begin
		
		dIn_neu <= dIn_temp + dIn_alt;
		
	
	end process Addiere;

	Flipflop: process (clk, din_neu)				-- Erzeugen des D-FlipFlop zum Zwischenspeichern --
	begin
		
		if clk ='1' and clk'event then
			Q <= din_neu after 40 ps;
			din_alt <= Q;
		
		else 
			Q <= "00000000000";
			
		end if;
	end process flipflop;
	
	--Hier ist das Problem, da man bei unsigned nicht das bit herausfiltern kann--

	Komperator: process (din_alt)					-- Herausfiltern des MSBit --
	begin
		
		
		dout_read <= din_alt (10);
		
		
	end process Komperator;
	
	Auffuellen: process (dout_read)					-- Erzeugen eines 10 Bit Vektors aus dem Bitstrom --
	begin
		
		case dout_read is
			when '0' => doutm <= "0000000000";
			when '1' => doutm <= "1111111111";
			

		end case;
	end process Auffuellen;
	
	dout <= std_logic (dout_read);

end Modulator;