-- Hier stehen die Bibliotheken library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; -- Beginn der Entity (Name der Entity ist bei der Testbench egal) entity TestTopSheet is end entity TestTopSheet; -- Beginn der Architektur architecture STIMULUS of TestTopSheet is -- Hier müssen die Ports vom Deinem TopSheet stehen component FPGA_Project port ( AUSGANG : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=AUSGANG CLK_9_MHZ : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=CLK_9_MHZ CLK_36_MHZ : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=CLK_36_MHZ CLR_BUTTON : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=CLR_BUTTON CS_ADC : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=CS_ADC CS_DAC : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=CS_DAC DATA_ADC : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=DATA_ADC DATA_DAC : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=DATA_DAC OUTPUT_ON : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=OUTPUT_ON SCLK_ADC : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=SCLK_ADC SCLK_DAC : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=SCLK_DAC TRIGGER : In STD_LOGIC -- ObjectKind=Port|PrimaryId=TRIGGERN ); end component; -- Hier erzeugst Du Signale können den gleichen Namen haben aber ist besser -- wenn man Sie kennzeichnet z.B. S_AUSGANG signal AUSGANG : STD_LOGIC; signal CLK_9_MHZ : STD_LOGIC; -- ObjectKind=Port|PrimaryId=CLK_9_MHZ signal CLK_36_MHZ : STD_LOGIC; -- ObjectKind=Port|PrimaryId=CLK_36_MHZ signal CLR_BUTTON : STD_LOGIC; -- ObjectKind=Port|PrimaryId=CLR_BUTTON signal CS_ADC : STD_LOGIC; signal CS_DAC : STD_LOGIC; signal DATA_ADC : STD_LOGIC; signal DATA_DAC : STD_LOGIC; -- ObjectKind=Port|PrimaryId=DATA_DAC signal OUTPUT_ON : STD_LOGIC; -- ObjectKind=Port|PrimaryId=OUTPUT_ON signal SCLK_ADC : STD_LOGIC; signal SCLK_DAC : STD_LOGIC; signal TRIGGER : STD_LOGIC; -- ObjectKind=Port|PrimaryId=TRIGGER signal REGF : STD_LOGIC_VECTOR(17 downto 0); signal ADC_SIGNAL : STD_LOGIC_VECTOR(11 downto 0); constant PERIOD: TIME:=27.77777777ns; -- Wichtig hier weist Du dem Port das Signal zu (MUT = Model under Test) begin MUT : FPGA_Project port map ( AUSGANG => AUSGANG, CLK_9_MHZ => CLK_9_MHZ, CLK_36_MHZ => CLK_36_MHZ, CLR_BUTTON => CLR_BUTTON, CS_ADC => CS_ADC, CS_DAC => CS_DAC, DATA_ADC => DATA_ADC, DATA_DAC => DATA_DAC, OUTPUT_ON => OUTPUT_ON, SCLK_ADC => SCLK_ADC, SCLK_DAC => SCLK_DAC, TRIGGER => TRIGGER ); -- ab hier starten Die Prozesse mit denen Du Deinen Testsignal erzeugst P1: PROCESS begin TRIGGER <= '0'; OUTPUT_ON <= '0'; CLR_BUTTON <= '1'; wait for 225 ns; OUTPUT_ON <= '1'; CLR_BUTTON <= '0'; TRIGGER <= '1'; wait for 60000ns; TRIGGER <= '0'; wait for 10000ns; TRIGGER <= '1'; wait; END PROCESS P1; P2: PROCESS begin CLK_9_MHZ <= '1'; wait for 55.555555ns; -- 9MHz Clock CLK_9_MHZ <= '0'; wait for 55.555555ns; END PROCESS P2; P3: PROCESS begin CLK_36_MHZ <= '1'; wait for PERIOD/2; -- 36MHz Clock CLK_36_MHZ <= '0'; wait for PERIOD/2; END PROCESS P3; P4: PROCESS(CLR_BUTTON,CLK_9_MHZ,REGF) begin if(CLR_BUTTON = '1')then REGF <= "000000000000000001"; elsif(CLK_9_MHZ 'event and CLK_9_MHZ = '0')then REGF <= REGF(16 downto 0) & REGF(17); end if; END PROCESS P4; P5: PROCESS(CLR_BUTTON,CLK_9_MHZ,REGF,ADC_SIGNAL) variable up : integer range 0 to 1; begin if(CLR_BUTTON = '1')then ADC_SIGNAL <= "000000000000"; up := 1; elsif(CLK_9_MHZ 'event and CLK_9_MHZ = '1')then if(REGF(1) = '1' and up = 1)then ADC_SIGNAL <= ADC_SIGNAL + 1; end if; if(REGF(1) = '1' and up = 0)then ADC_SIGNAL <= ADC_SIGNAL - 1; end if; if(REGF(2) = '1' and ADC_SIGNAL(3) = '1')then up := NOT up; end if; end if; END PROCESS P5; P6: PROCESS(CLR_BUTTON,CLK_36_MHZ,REGF,ADC_SIGNAL) begin if(CLR_BUTTON = '1')then DATA_ADC <= '0'; elsif(CLK_36_MHZ 'event and CLK_36_MHZ = '1')then case REGF is when "000000000000100000" => DATA_ADC <= ADC_SIGNAL(11); when "000000000001000000" => DATA_ADC <= ADC_SIGNAL(10); when "000000000010000000" => DATA_ADC <= ADC_SIGNAL(9); when "000000000100000000" => DATA_ADC <= ADC_SIGNAL(8); when "000000001000000000" => DATA_ADC <= ADC_SIGNAL(7); when "000000010000000000" => DATA_ADC <= ADC_SIGNAL(6); when "000000100000000000" => DATA_ADC <= ADC_SIGNAL(5); when "000001000000000000" => DATA_ADC <= ADC_SIGNAL(4); when "000010000000000000" => DATA_ADC <= ADC_SIGNAL(3); when "000100000000000000" => DATA_ADC <= ADC_SIGNAL(2); when "001000000000000000" => DATA_ADC <= ADC_SIGNAL(1); when "010000000000000000" => DATA_ADC <= ADC_SIGNAL(0); when others => NULL; end case; end if; END PROCESS P6; END STIMULUS;