library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is 
port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
RST: out STD_LOGIC;
CE, LOAD, DIR: in STD_LOGIC;
DIN: in STD_LOGIC_VECTOR(3 downto 0);
TEST: out STD_LOGIC_VECTOR(3 downto 0));		-- only "out"
end counter;

architecture Behavioral of counter is
SIGNAL next_state	: std_logic_vector (3 downto 0);
begin

process(CLK, RESET, LOAD, DIN, CE, DIR)
variable count	: std_logic_vector (3 downto 0);
begin
   
if (DIR='1') then			-- construction of a look-up-table for the next state when counting up
case count is
	when "1001" => next_state<="0000";
	when others	 => next_state<=count+1; 
end case;
end if;

if (DIR='0') then			-- construction of a look-up-table for the next state when counting down
case count is
	when "0000" => next_state<="1001";
	when others	 => next_state<=count-1; 
end case;
end if;	 


	if ((RESET and DIR)='1') then	  --	Reset has the first priority
		count:="0000";
	elsif (RESET='1' and DIR='0')	then
		count:="1001";
	elsif (Load='1') then			  -- Load: second priority
	count:=DIN;
	elsif (CLK='1' and CLK'event)	then 	-- Rising clock
		if (CE='1') then					   --	has the function of the clock-enable
		count:=next_state;					-- counting
   	RST <='0';								-- you wrote this in your code, I have no idea what it means because it doesn't make sense!
		end if;
	end if;
TEST<=count;								-- connecting internal state-buffer (count) with the pins 
end process;

end Behavioral;