library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pwm is
 Port (	
 
 	sclk : in std_logic;
   sdata : in std_logic_vector(3 downto 0);
	sel	: in std_logic_vector(2 downto 0);
	clock : in std_logic;
	reset : in std_logic;
	pwm1 : out std_logic;
   pwm2 : out std_logic;
	pwm3 : out std_logic;
   pwm4 : out std_logic;			  
	pwm5 : out std_logic;
 	pwm6 : out std_logic;			  
	pwm7 : out std_logic;
   pwm8 : out std_logic);
end pwm;

architecture Behavioral of pwm is
	-------------------------------
	-- Define Internal Signal
	-------------------------------
	signal PWMW1: STD_LOGIC_VECTOR (3 downto 0);  --Output of Shift Register
	signal PWMW2: STD_LOGIC_VECTOR (3 downto 0);  --Output of Shift Register
	signal PWMW3: STD_LOGIC_VECTOR (3 downto 0);  --Output of Shift Register
	signal PWMW4: STD_LOGIC_VECTOR (3 downto 0);  --Output of Shift Register
	signal PWMW5: STD_LOGIC_VECTOR (3 downto 0);  --Output of Shift Register
	signal PWMW6: STD_LOGIC_VECTOR (3 downto 0);  --Output of Shift Register
	signal PWMW7: STD_LOGIC_VECTOR (3 downto 0);  --Output of Shift Register
	signal PWMW8: STD_LOGIC_VECTOR (3 downto 0);  --Output of Shift Register

	signal PWMC: Integer range 0 to 15;

	----------------------------------------------
type  Memory is array (7 downto 0) of std_logic_vector (3 downto 0);
begin

mem_ac : PROCESS (sel, sclk, sdata, reset)
variable Field	: Memory;
begin

if (reset='1') then
	for i in 0 to 7 loop
	Field(i):=(others=>'0');
	end loop;
	elsif (sclk='1' and sclk'event) then
		Field(conv_integer(sel)):=sdata; 
end if;

PWMW1<=Field(0);
PWMW2<=Field(1);
PWMW3<=Field(2);
PWMW4<=Field(3);
PWMW5<=Field(4);
PWMW6<=Field(5);
PWMW7<=Field(6);
PWMW8<=Field(7);

end process mem_ac;

	--------------------------------
	process (clock) begin
		if (clock' event and clock = '1') then
			PWMC <= PWMC +1;
		end if;
	end process;

	process (PWMC,PWMW1) begin
		if (PWMC < PWMW1) then
			pwm1 <= '0';	
		else 
			pwm1 <= '1';	
		end if;
	end process;

	process (PWMC,PWMW2) begin
		if (PWMC < PWMW2) then
			pwm2 <= '0';	
		else 
			pwm2 <= '1';	
		end if;
	end process;

	process (PWMC,PWMW3) begin
		if (PWMC < PWMW3) then
			pwm3 <= '0';	
		else 
			pwm3 <= '1';	
		end if;
	end process;

	process (PWMC,PWMW4) begin
		if (PWMC < PWMW4) then
			pwm4 <= '0';	
		else 
			pwm4 <= '1';	
		end if;
	end process;

	process (PWMC,PWMW5) begin
		if (PWMC < PWMW5) then
			pwm5 <= '0';	
		else 
			pwm5 <= '1';	
		end if;
	end process;

	process (PWMC,PWMW6) begin
		if (PWMC < PWMW6) then
			pwm6 <= '0';	
		else 
			pwm6 <= '1';	
		end if;
	end process;

	process (PWMC,PWMW7) begin
		if (PWMC < PWMW7) then
			pwm7 <= '0';	
		else 
			pwm7 <= '1';	
		end if;
	end process;

	process (PWMC,PWMW8) begin
		if (PWMC < PWMW8) then
			pwm8 <= '0';	
		else 
			pwm8 <= '1';	
		end if;
	end process;

end Behavioral;