library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity pwm is port( sclk: in std_logic; sdata: in std_logic_vector(3 downto 0); sel: in std_logic_vector(2 downto 0); clock: in std_logic; reset: in std_logic; pins: buffer std_logic_vector(7 downto 0) ); end; architecture Behavioral of pwm is type registers is array(7 downto 0) of std_logic_vector(3 downto 0); signal pwm_reg: registers; signal counter: std_logic_vector(3 downto 0); begin process(sel, sclk, sdata, reset) begin if reset = '1' then for i in 0 to 7 loop pwm_reg(i) <= (others => '0'); end loop; else if sclk'event and sclk = '1' then pwm_reg(conv_integer(sel)) <= sdata; end if; end if; end process; process(clock) begin if clock' event and clock = '1' then -- if counter = "0000" then -- pins <= (others => '0'); -- else -- for i in 0 to 7 loop -- if counter = pwm_reg(i) then -- pins(i) <= not pins(i); -- end if; -- end loop; -- end if; for i in 0 to 7 loop if counter < pwm_reg(i) then pins(i) <= '0'; else pins(i) <= '1'; end if; end loop; counter <= counter +1; end if; end process; end Behavioral;