--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    18:48:30 04/27/05
-- Design Name:    
-- Module Name:    dec - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--BLITZ-ADRESS-DECODER
ENTITY blitz_adress_decoder IS
	PORT(
		ale					: IN	STD_LOGIC;   					--Adress Latch Enable
		res					: IN	STD_LOGIC;	 					--Reset
		wr					: IN	STD_LOGIC;   					--Write Enable
		rd					: IN	STD_LOGIC;   					--Read Enable
		
		ad7_0_inout			: INOUT	STD_LOGIC_VECTOR(7 DOWNTO 0);	--Adresse (Low) und Datenbus (Multiplex)
		a23_8_in			: IN	STD_LOGIC_VECTOR(7 DOWNTO 0);	--Adressbus (Middle und High)(Multiplex) 
		in_port				: IN	STD_LOGIC_VECTOR(7 DOWNTO 0);	--Eingangsport
		
		reset				: OUT	STD_LOGIC;   					--Reset erzeugen
		cs_ram				: OUT	STD_LOGIC;   					--Ram adressieren
		cs_lcd				: OUT	STD_LOGIC;   					--LCD adressieren
		isp					: OUT	STD_LOGIC;   					--In System Programming aktivieren
		a16_out				: OUT	STD_LOGIC;   					--Adress-Bit 16 (für 128k RAM)
		
		a7_0_out			: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0); 	--Adresse (Low)
		out_port			: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0); 	--Ausgangsport
		
		rxd_p				: OUT	STD_LOGIC;   					--serielles Signal zum Prozessor
		txd_p				: IN	STD_LOGIC;   					--serielles Signal vom Prozessor
		rxd_485				: IN	STD_LOGIC;   					--serielles Signal von RS485
		txd_485				: OUT	STD_LOGIC;   					--serielles Signal zur RS485
		rxd_232				: IN	STD_LOGIC;   					--serielles Signal von RS232
		txd_232				: OUT	STD_LOGIC;   					--serielles Signal zur RS232
		rxd_232m			: IN	STD_LOGIC;   					--serielles Signal von RS232 (Pegelwandler auf MC-Modul)
		txd_232m			: OUT	STD_LOGIC   					--serielles Signal zur RS232 (Pegelwandler auf MC-Modul)

		);
END blitz_adress_decoder;



ARCHITECTURE verhalten OF blitz_adress_decoder IS

--komplettes 17Bit-Adress-Signal zur Erzeugung der Chip-Selects 
SIGNAL adr16_0		: STD_LOGIC_VECTOR(16 DOWNTO 0);
--interne Chip-Select-Signale 
SIGNAL cs_outport	: STD_LOGIC;	
SIGNAL cs_inport	: STD_LOGIC;
SIGNAL cs_ctrl		: STD_LOGIC;
--Auswahl UART
SIGNAL uart_select  : STD_LOGIC_VECTOR(1 DOWNTO 0);

	
BEGIN

	--Adress-Latch
	process(ale,res,adr16_0,a23_8_in)
	begin
				
		if res  = '0' then
			adr16_0		<= (others=> '0');
	
		elsif ale='1' then
			adr16_0(7  downto  0)	<= ad7_0_inout;	--Low-Byte
			adr16_0(16)				<= a23_8_in(0);	--16. Adress-Bit
		end if;
	end process;

adr16_0(15 downto 8)	<= a23_8_in;		--High-Byte
		
--gelatchte Adresse an Ausgangspins
a7_0_out	<=	adr16_0(7 downto 0);
a16_out		<=	adr16_0(16);


cs_ram<='0' when adr16_0(16)='1' else '1';
cs_lcd<='0' when adr16_0=B"0" & X"FFFF" else '1';    
cs_outport<='0' when adr16_0=B"0" & X"FFFE" else '1';
cs_inport<='0' when adr16_0=B"0" & X"FFFD" else '1';
cs_ctrl<='0' when adr16_0=B"0" & X"FFFC" else '1';  	
	
	--Adress-Dekodierung
--	process(res,adr16_0)
--	begin
--				
--		if res  = '0' then
--			cs_lcd		<= 	'1';
--			cs_outport	<= 	'1';
--			cs_inport	<= 	'1';
--			cs_ctrl   	<= 	'1';
--			cs_ram		<= 	'1';
--		
--		--LCD			
--		elsif adr16_0 >=	B"0" & X"FFFD" then
--			cs_lcd		<= 	'0';
--			cs_outport	<= 	'1';
--			cs_inport	<= 	'1';
--			cs_ctrl		<= 	'1';
--			cs_ram		<= 	'1';
--		
--		--Ausgangs-Port	
--		elsif adr16_0				=	B"0" & X"FFFC" then
--			cs_lcd		<= 	'1';
--			cs_outport	<= 	'0';
--			cs_inport	<= 	'1';
--			cs_ctrl		<= 	'1';
--			cs_ram		<= 	'1';
--		
--		--Eingangs-Port	
--		elsif adr16_0				=	B"0" & X"FFFB" then
--			cs_lcd		<= 	'1';
--			cs_outport	<= 	'1';
--			cs_inport	<= 	'0';
--			cs_ctrl		<= 	'1';
--			cs_ram		<= 	'1';
--		
--		--Latch für ISP- und Reset-Signal	
--		elsif adr16_0				=	B"0" & X"FFFA" then
--			cs_lcd		<= 	'1';
--			cs_outport	<= 	'1';
--			cs_inport	<= 	'1';
--			cs_ctrl		<= 	'0';
--			cs_ram		<= 	'1';
--		
--		--für alle anderen Adressen wird das RAM selektiert	
--		else
--			cs_lcd		<= 	'1';
--			cs_outport	<= 	'1';
--			cs_inport	<= 	'1';
--			cs_ctrl		<= 	'1';
--			cs_ram		<= 	'0';
--
--		end if;
--			
--	end process;


	--Output_Port
	process(res,cs_outport,wr,ad7_0_inout)
	begin
	
		if res  = '0' then
			out_port	<= 	X"07"; 
		elsif  cs_outport = '0'	and wr = '0' then
			out_port	<=	ad7_0_inout;
		end if;
			
	end process;
	
	
	--Input_Port
	process(cs_inport,rd,in_port)
	begin		
	
		if  cs_inport = '0'	and rd = '0' then
			ad7_0_inout	<=	in_port;
		else
			ad7_0_inout <=  (others=> 'Z');
		end if;

	end process;
	
	
	--Control-Register
	process(res,cs_ctrl,wr,ad7_0_inout)
	begin
	
		if res  = '0' then
			reset		<= 	'1';
			isp			<= 	'0';
			uart_select	<= (others=> '0');			
		elsif  cs_ctrl = '0'	and falling_edge(wr) then
			reset		<=	ad7_0_inout(0);
			isp			<=	ad7_0_inout(1);
			uart_select	<=	ad7_0_inout(3 downto 2);			
		end if;
			
	end process;


	--RS232 oder RS485 - Auswahl
	process(uart_select,txd_p,rxd_232m,rxd_232,rxd_485)
	begin	
	
	case (uart_select) is
		when "00" => rxd_p     <= rxd_232m;	
						 txd_232m  <= txd_p;		
		when "01" => rxd_p     <= rxd_232;	
						 txd_232   <= txd_p;
		when "10" => rxd_p     <= rxd_485;	
						 txd_485   <= txd_p;
		when others =>	rxd_p     <= rxd_232m;	
						   txd_232m  <= txd_p;

	end case;	
	end process;

END verhalten;