----------------------------------------------------------------------------
FPGA 1 (Virtex II Pro)
----------------------------------------------------------------------------
UCF:

NET "CLK_P" TNM_NET = "CLK_P";
TIMESPEC "TS_CLK_P" = PERIOD "CLK_P" 101 MHz HIGH 50 % INPUT_JITTER 0.25 ns;
NET "CLK_N" TNM_NET = "CLK_N";
TIMESPEC "TS_CLK_N" = PERIOD "CLK_N" 101 MHz HIGH 50 % INPUT_JITTER 0.25 ns;

NET "CLK_N" 					LOC = "D17";
NET "CLK_P" 					LOC = "E17";

NET "HDA_CLK"					IOSTANDARD = LVTTL | DRIVE = 16 | SLEW = FAST;
NET "HDB_CLK"					IOSTANDARD = LVTTL | DRIVE = 16 | SLEW = FAST;

-----------------------------------------------------------------------------

-- ENTITY FPGA 1

-- Differential Clock
CLK_N			: in  std_logic;
CLK_P			: in  std_logic;			 			 
-- LVDS-Bus A-Side
HDA_CLK			: out std_logic;
-- LVDS-Bus B-Side
HDB_CLK			: out std_logic;

-- ARCHITECTURE FPGA 1

component dcm is
port( 
	CLKIN_N_IN        : in  std_logic; 
    CLKIN_P_IN        : in  std_logic; 
    RST_IN            : in  std_logic; 
    CLKIN_IBUFGDS_OUT : out std_logic; 
    CLK0_OUT          : out std_logic; 
    LOCKED_OUT        : out std_logic);
end component;

i_dcm: dcm
port map( 
	CLKIN_N_IN   		=> CLK_N, 
    CLKIN_P_IN       	=> CLK_P,
    RST_IN           	=> c_logic0,
    CLKIN_IBUFGDS_OUT 	=> open,
    CLK0_OUT         	=> s_clk,
    LOCKED_OUT       	=> s_reset);

U_DDR_HDA_CLK : FDDRRSE
PORT MAP (
      Q  => s_hda_clk,
      C0 => s_clk,
      C1 => s_clkn,
      CE => c_logic1,
      D0 => c_logic1,
      D1 => c_logic0,
      R  => c_logic0,
      S  => c_logic0);
   
U_DDR_HDB_CLK : FDDRRSE
PORT MAP (
      Q  => s_hdb_clk,
      C0 => s_clk,
      C1 => s_clkn,
      CE => c_logic1,
      D0 => c_logic1,
      D1 => c_logic0,
      R  => c_logic0,
      S  => c_logic0);

HDA_CLK  <= s_hda_clk;
HDB_CLK  <= s_hdb_clk;

-----------------------------------------------------------------------	
FPGA 2: (Spartan 2)
-----------------------------------------------------------------------

UCF:

NET "CLK_IN"	LOC = "N8";
NET "CLK_IN"	IOSTANDARD = LVTTL;

NET "CLK_IN" TNM_NET = "CLK_IN";
TIMESPEC "TS_CLK_IN" = PERIOD "CLK_IN" 101 MHz HIGH 50 %;

ENTITY FPGA 2:

CLK_IN 	: in  std_logic;

ARCHITECTURE FPGA 2:

component IBUFG port
		(   O 		: out std_logic;
		    I 		: in std_logic);
end component;
	
component BUFG port
		(   O 		: out std_logic;
		    I 		: in std_logic);
end component;
	
component CLKDLL 
	port	
		(   CLKIN 	: in std_logic;
			CLKFB 	: in std_logic;
			RST   	: in std_logic;
			CLK0  	: out std_logic;	-- Feedback Clock
			CLK90	: out std_logic;	-- open
			CLK180  : out std_logic;	-- open
			CLK270  : out std_logic;	-- open
			CLK2X   : out std_logic;	-- open
			CLKDV   : out std_logic;    -- open 
			LOCKED	: out std_logic); 
end component;

i_IBUFG_1 : IBUFG
    PORT MAP (
      O 			=> sl_clk_in_ibufg,
      I 			=> s_clk_in);
		
i_BUFG_1 : BUFG
    PORT MAP (
      O 			=> sl_clk_out_bufg,
      I 			=> sl_clk_out_dll);	

i_CLKDLL_FPGA : CLKDLL        
    PORT MAP (
      CLKIN  	=> sl_clk_in_ibufg,		
      CLKFB  	=> sl_clk_out_bufg,		
      RST    	=> s_resetn_async,				
      CLK0   	=> sl_clk_out_dll,		
	  CLK90	 	=> open,					
	  CLK180 	=> open,					
	  CLK270 	=> open,					
	  CLK2X  	=> open,
	  CLKDV  	=> open,
      LOCKED 	=> sl_locked_dll);
	  
s_clk_in		<= CLK_IN;