library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity lcd_daten_tb is end entity lcd_daten_tb; architecture testbench of lcd_daten_tb is constant clk_period : time := (1 sec)/(50_000_000) ; constant tAH6 : time := 20 ns; constant tAW6 : time := 20 ns; constant tCYC6 : time := 400 ns; constant tDS6 : time := 100 ns; constant tDH6 : time := 40 ns; constant tEWH : time := 200 ns; constant tEWL : time := 150 ns; component lcd_daten is port( clk : in std_logic; --reset : in std_logic:= '1'; o_rs : out std_logic; o_rw : out std_logic; o_e : out std_logic; o_csb : out std_logic; o_cs : out std_logic; o_data : out std_logic_vector(7 downto 0) ); end component lcd_daten; signal tb_clk : std_logic := '1'; signal tb_reset : std_logic := '1'; signal tb_o_rs : std_logic; signal tb_o_rw : std_logic; signal tb_o_e : std_logic; signal tb_o_csb : std_logic; signal tb_o_cs : std_logic; signal tb_o_data : std_logic_vector(7 downto 0); begin dut: lcd_daten port map ( clk => tb_clk, -- : in std_logic; --reset => tb_reset, -- : in std_logic:= '1'; o_rs => tb_o_rs, -- : out std_logic; o_rw => tb_o_rw, -- : out std_logic; o_e => tb_o_e, -- : out std_logic; o_csb => tb_o_csb, -- : out std_logic; o_cs => tb_o_cs, -- : out std_logic; o_data => tb_o_data -- : out std_logic_vector(7 downto 0) ); tb_clk <= not tb_clk after clk_period/2; tb_reset <= '0', '1' after 5*clk_period; -- timing checker process variable change:time; begin wait until tb_o_rs'event; change := now; wait until rising_edge( tb_o_e); assert (now - change) >= tAW6 report "Address setup time to short (RS)"; end process; process variable change:time; begin wait until falling_edge( tb_o_e); change := now; wait until tb_o_rs'event; assert (now - change) >= tAH6 report "Address hold time to short (RS)"; end process; process variable change:time; begin wait until tb_o_rw'event; change := now; wait until rising_edge( tb_o_e); assert (now - change) >= tAW6 report "Address setup time to short (RW)"; end process; process variable change:time; begin wait until falling_edge( tb_o_e); change := now; wait until tb_o_rw'event; assert (now - change) >= tAH6 report "Address hold time to short (RW)"; end process; process variable change:time; begin wait until tb_o_data'event; change := now; wait until falling_edge( tb_o_e); assert (now - change) >= tDS6 report "Data setup time to short"; end process; process variable change:time; begin wait until falling_edge( tb_o_e); change := now; wait until tb_o_data'event; assert (now - change) >= tDH6 report "Data hold time to short"; end process; process variable change:time; begin wait until rising_edge( tb_o_e); change := now; wait until falling_edge( tb_o_e); assert (now - change) >= tEWH report "Enable H pulse time to short"; end process; process variable change:time; begin wait until falling_edge( tb_o_e); change := now; wait until rising_edge( tb_o_e); assert (now - change) >= tEWL report "Enable L pulse time to short"; end process; process variable change:time; begin wait until rising_edge( tb_o_e); change := now; wait until rising_edge( tb_o_e); assert (now - change) >= tCYC6 report "System cycle time to short"; end process; process variable rs_string: string(1 to 11); variable rw_string: string(1 to 11); begin wait until falling_edge( tb_o_e); if tb_o_rw = '1' then rw_string := "read "; end if; if tb_o_rw = '0' then rw_string := "write "; end if; if tb_o_rs = '1' then rs_string := "instruction"; end if; if tb_o_rs = '0' then rs_string := "data "; end if; report rw_string & " to " & rs_string & " register: " & integer'image( to_integer( unsigned(tb_o_data))) & " (" & character'val( to_integer( unsigned(tb_o_data))) & ")" severity note; end process; end testbench;