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-- Company: 
-- Engineer:
--
-- Create Date:    13:38:47 11/07/10
-- Design Name:    
-- Module Name:    timer - Behavioral
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
---	>>>>>	t_clk		clock in for counting
---	>>>>>	t_reset		reset counter to 0
---	<<<<<	t_sec		8Bit output hold the second count result
---	<<<<<
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--------------------------------------------------------------------

ENTITY timer IS
	Port (clkin : IN std_logic;
			t_reset : in std_logic;
			t_sec :  out std_logic_vector(7 downto 0)
			);
END timer;

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ARCHITECTURE timer_logic OF timer IS

 COMPONENT te
  PORT(
    CLKIN_IN : IN std_logic;
    RST_IN : IN std_logic;
    CLKIN_IBUFG_OUT : OUT std_logic;
    CLK0_OUT : OUT std_logic;
    CLK2X_OUT : OUT std_logic;
    LOCKED_OUT : OUT std_logic
    );
  END COMPONENT;

signal sec_counter: std_logic_vector(7 downto 0);
signal counter: std_logic_vector(25 downto 0);


begin
			 
Inst_te: te PORT MAP(
    CLKIN_IN => clkin ,
    RST_IN => t_reset,
    CLKIN_IBUFG_OUT => null,
    CLK0_OUT => null,
    CLK2X_OUT => clk2x,
    LOCKED_OUT => null
  );

process(clk2x)
begin

if (clk2x='1' and clk2x'event) then 
counter <= counter + "1";
-------t_sec <= sec_counter;

 if (counter>"10111110101111000010000000") then
counter <=   "00000000000000000000000000";
sec_counter <= sec_counter +'1';
end if;

if (t_reset='1') then
 counter <= "00000000000000000000000000";
sec_counter <= "00000000";
t_sec <= "11000000";
end if;

end if; --clock event
end process;

end timer_logic;

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