-- t_conversion 	7.5 µs (max)
-- t_acquisition 	1,5 µs (max)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity AD_CONVERTER is
	generic ( CLK_DIVIDER : integer := 5 -- CLK divider
			);
    Port ( CLK_IN_EXT 	: in  std_logic;	-- CPLD Clock (10 MHz)
		     DOUT_IN_EXT  : in  std_logic; 	-- Serial output A/D converter  
           SCLK_OUT_EXT : out std_logic;	-- Serial-clock input (up to 2.1 MHz)
		   CS_OUT_EXT	: out std_logic	-- Activate-Low chip selcet; conversion statrs at falling edge 
			--AUSGANG_TEST : out std_logic
		   );
end AD_CONVERTER;


architecture Behavioral of AD_CONVERTER is

-- signals CLK_DIVIDER_PROCESS
signal SLOW_CLK 		: std_logic := '0';
signal PRESCALER 		: integer  range 0 to CLK_DIVIDER := 0;
-- signals READ_AD_PROCESS
signal READ_AD_COUNTER 	: integer range 0 to 63 := 0 ;
-- begin architecture
begin

--AUSGANG_TEST <= DOUT_IN_EXT;
-- Process produces a signal SLOW_CLK by dividing the CLK_IN_EXT clock
-- 10 MHz / 5 = 2 MHz ^= 500 ns => Periodendauer von SCLK 1000 ns d.h. nur 1 MHz (für Testzwecke gut!)
CLK_DIVIDER_PROCESS : process 
begin
	wait until rising_edge (CLK_IN_EXT);
		SLOW_CLK <= '0';
		if (PRESCALER = CLK_DIVIDER - 1) then
			PRESCALER <= 0;
			SLOW_CLK <= '1'; 
		else
			PRESCALER <= PRESCALER + 1;
		end if;
end process CLK_DIVIDER_PROCESS;


-- SCLK wird mit halbem Takt von SLOW_CLK ausgegeben!!
READ_AD_PROCESS : process
begin
	wait until rising_edge (CLK_IN_EXT);
		if (SLOW_CLK = '1') then
			-- step 1
			-- start convertion process
	
	-- 0ns	
			if (READ_AD_COUNTER = 0) then
				CS_OUT_EXT <= '0'; 
				SCLK_OUT_EXT <= '0';
			-- step 2
			-- wait maximum conversion time (7.5 µs (max))
			-- => 7,5µs ^= 7500ns ^= READ_AD_COUNTER = 15
			-- step 3
			-- activate SCLK for a minimum of 11 clock cycles.
	
	-- 8000ns
			elsif (READ_AD_COUNTER = 16) then
				SCLK_OUT_EXT <= '1';
	
	-- 8500ns until 18500ns
			elsif (READ_AD_COUNTER >= 17 and READ_AD_COUNTER < 37) then
				if (READ_AD_COUNTER mod 2 = 1) then
					SCLK_OUT_EXT <= '0';
				
				else 
					SCLK_OUT_EXT <= '1';
					-- DATA_OUT <= DATA_OUT(7 downto 1) & DOUT_IN_EXT;
				
				end if;
	
	-- 19000ns
			-- step 4 Pull CS high and wait tCS (240 ns)
			elsif (READ_AD_COUNTER = 37) then		
				CS_OUT_EXT <= '1'; 
				SCLK_OUT_EXT <= '0';
			end if;
			
			if (READ_AD_COUNTER >= 40) then
				READ_AD_COUNTER <= 0;
			else
				READ_AD_COUNTER <= READ_AD_COUNTER + 1;
			end if;
		end if; --if (SLOW_CLK = '1') then
end process READ_AD_PROCESS;
 
end Behavioral;