Status-Register NZCIxxxx Negative-Flag Zero-Flag Carry-Flag Interrupt-Flag FFFF Condition Register UUUUCNZ1 4321FFF- Ctrl-Opcodes : 0c00 0000 0ccc 0000 0000 Nop 0c10 0000 0ccc 0001 0000 Cond. Halt 0c18 0000 0ccc 0001 1000 Cond. Drop Mark 0c2y 0000 0ccc 0010 yyyy Cond. Test Register y 0c3y 0000 0ccc 0011 yyyy Cond. Trap y 0c40 0000 0ccc 0100 0000 Cond. Return From Subroutine 0c48 0000 0ccc 0100 1000 Cond. Return From Interrupt 0c50 0000 0ccc 0101 0yyy Cond. Jump to Last Mark when Cond. y (loop) is met 0c58 0000 0ccc 0101 1yyy Cond. Jump to Last Mark when Cond. y (loop) is not met 0c6y 0000 0ccc 0110 0yyy Cond. Clr Condition-Reg Bit y 0c6y 0000 0ccc 0110 1yyy Cond. Set Condition-Reg Bit y 0c7y 0000 0ccc 0111 0yyy Cond. Clr Status-Reg Bit y 0c7y 0000 0ccc 0111 1yyy Cond. Set Status-Reg Bit y 0c8y 0000 0ccc 1000 yyyy Cond. Push Reg y on Stack 0c9y 0000 0ccc 1001 yyyy Cond. Pop Reg y from Stack 0cay 0000 0ccc 1010 yyyy Cond. Jump To Addr [Register y (lo)] 0cby 0000 0ccc 1011 yyyy Cond. Jump To Subroutine Addr [Register y (lo)] 0ccy 0000 0ccc 1100 yyyy Cond. Swap Hi/Lo-Byte of Register y 0ccy 0000 0ccc 1101 yyyy Cond. Swap Hi/Lo-Nibble of Lo-Byte of Register y 0cdy 0000 0ccc 1110 yyyy Cond. Clear Register y 0cxy 0000 1ccc 0xxx yyyy Cond. Inc/Dec Register y with Mode x (1/2/4/8+p/n) 1cxy 0001 0ccc xxxx yyyy Cond. Writes Register y to IO-Reg [Register x] 1cxy 0001 1ccc xxxx yyyy Cond. Reads from IO-Reg [Register x] to Register y Condition-Processing 2dab 0010 00dd xaaa ybbb AND-Condition aaa/bbb = Condition, x/y = Invert Condition, dd -> Destination User Con. 2dab 0010 01dd xaaa ybbb OR-Condition aaa/bbb = Condition, x/y = Invert Condition, dd -> Destination User Con. 2dab 0010 10dd xaaa ybbb XOR-Condition aaa/bbb = Condition, x/y = Invert Condition, dd -> Destination User Con. 2dab 0010 11dd xxxx yyyy Load Bit [Register x] from Register y to Cond. d 3cxy 0011 aadd xxxx yyyy Compare X & Y upon Condition a store it in C-Reg d Move-Opcodes : 4cxy 0100 0ccc xxxx yyyy Cond. Move Register x -> Register y 4cxy 0100 1ccc xxxx yyyy Cond. Move Register y -> Addr [Register x] 5cxy 0101 0ccc xxxx yyyy Cond. Move Addr [Register x] -> Register y 5c0y 0101 1ccc 0000 yyyy Cond. Move ACC-Lo -> Register y 5c1y 0101 1ccc 0001 yyyy Cond. Move Register y -> ACC-Lo 5c2y 0101 1ccc 0010 yyyy Cond. Move ACC-Hi -> Register y 5c3y 0101 1ccc 0011 yyyy Cond. Move Register y -> ACC-Hi 5c4y 0101 1ccc 0100 yyyy Cond. Move PC-Lo -> Register y 5c5y 0101 1ccc 0101 yyyy Cond. Move Register y -> PC-Lo 5c6y 0101 1ccc 0110 yyyy Cond. Move SP-Lo -> Register y 5c7y 0101 1ccc 0111 yyyy Cond. Move Register y -> SP-Lo 6xdd 0110 dddd dddd yyyy Cond. Move Hi-Byte d -> Register y 7xdd 0111 dddd dddd yyyy Cond. Move Lo-Byte d -> Register y ALU-Opcodes : 8cxy 1000 0ccc xxxx yyyy Cond. Add Reg x & Reg y -> Store in acc 8cxy 1000 1ccc xxxx yyyy Cond. Sub Reg x & Reg y -> Store in acc 9cxy 1001 0ccc xxxx yyyy Cond. Mul Reg x & Reg y -> Store in acc, acc + 1 9cxy 1001 1ccc xxxx yyyy Cond. And Reg x & Reg y -> Store in acc Acxy 1010 0ccc xxxx yyyy Cond. Or Reg x & Reg y -> Store in acc Acxy 1010 1ccc xxxx yyyy Cond. Xor Reg x & Reg y -> Store in acc Bcxy 1011 0ccc xxxx yyyy Cond. SHR Reg x & Reg y -> Store in Reg x Bcxy 1011 1ccc xxxx yyyy Cond. SHL Reg x & Reg y -> Store in Reg x ccc -> Condition aus dem Condition Register 000 -> always 001 -> zero-flag (vom Status-Reg) 010 -> negative-flag (vom Status-Reg) 011 -> carry-flag (vom Status-Reg) 100-111 -> user-flags (compare&logic&bits) aa -> Compare 00 -> EQ 01 -> GR 10 -> LS 11 -> NE Mark/Loop Überlegung Mark -> (PC -> Stack),(PC -> Topmost) Loop -> cond2 = '1' ? (Topmost -> PC) : (pull Topmost) Push -> (Arg -> Stack) (Arg -> Topmost) Pull -> (pull Arg) (pull Topmost) SP++ - = Stackpointer - .. - .. - Mark -- ... -- ... -- Call --- ... --- ... --- Ret -- .. -- Loop - .. - ..