LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY rgb_rechner IS PORT ( y, cb, cr : IN STD_LOGIC_VECTOR (7 DOWNTO 0); r, g, b : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)); END rgb_rechner; ARCHITECTURE behaviour OF rgb_rechner IS BEGIN PROCESS (y, cb, cr) VARIABLE r_lang, g_lang, b_lang : unsigned (15 DOWNTO 0); BEGIN r_lang := (1164 * (unsigned(y) - 16)) + (1596 * (unsigned(cr) - 128)); g_lang := (1164 * (unsigned(y) - 16)) - (0392 * (unsigned(cb) - 128)) + (0813 * (unsigned(cr) - 128)); b_lang := (1164 * (unsigned(y) - 16)) + (2017 * (unsigned(cb) - 128)) ; r <= std_logic_vector(r_lang (14 DOWNTO 5)); g <= std_logic_vector(g_lang (14 DOWNTO 5)); b <= std_logic_vector(b_lang (14 DOWNTO 5)); END PROCESS; END behaviour; LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY wrapper IS PORT ( clk : IN STD_LOGIC; y, cb, cr : IN STD_LOGIC_VECTOR (7 DOWNTO 0); r, g, b : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)); END wrapper; ARCHITECTURE behaviour OF wrapper IS component rgb_rechner IS PORT ( y, cb, cr : IN STD_LOGIC_VECTOR (7 DOWNTO 0); r, g, b : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)); END component; signal ly, lcb, lcr : STD_LOGIC_VECTOR (7 DOWNTO 0); signal lr, lg, lb : STD_LOGIC_VECTOR (9 DOWNTO 0); BEGIN calc: rgb_rechner Port map ( y => ly, cb => lcb, cr => lcr, r => lr, g => lg, b => lb ); process begin wait until rising_edge(clk); ly <= y; lcr <= cr; lcb <= cb; r <= lr; g <= lg; b <= lb; end process; END behaviour;