sternenhimmel.elf: file format elf32-avr Sections: Idx Name Size VMA LMA File off Algn 0 .text 00000544 00000000 00000000 00000094 2**1 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .data 00000004 00800060 00000544 000005d8 2**0 CONTENTS, ALLOC, LOAD, DATA 2 .bss 0000003f 00800064 00800064 000005dc 2**0 ALLOC 3 .debug_aranges 00000060 00000000 00000000 000005dc 2**0 CONTENTS, READONLY, DEBUGGING 4 .debug_pubnames 0000015a 00000000 00000000 0000063c 2**0 CONTENTS, READONLY, DEBUGGING 5 .debug_info 000004d9 00000000 00000000 00000796 2**0 CONTENTS, READONLY, DEBUGGING 6 .debug_abbrev 0000030d 00000000 00000000 00000c6f 2**0 CONTENTS, READONLY, DEBUGGING 7 .debug_line 00000494 00000000 00000000 00000f7c 2**0 CONTENTS, READONLY, DEBUGGING 8 .debug_frame 000000f0 00000000 00000000 00001410 2**2 CONTENTS, READONLY, DEBUGGING 9 .debug_str 000001e6 00000000 00000000 00001500 2**0 CONTENTS, READONLY, DEBUGGING 10 .debug_loc 00000139 00000000 00000000 000016e6 2**0 CONTENTS, READONLY, DEBUGGING 11 .debug_ranges 00000018 00000000 00000000 0000181f 2**0 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 00000000 <__vectors>: 0: 12 c0 rjmp .+36 ; 0x26 <__ctors_end> 2: 2c c0 rjmp .+88 ; 0x5c <__bad_interrupt> 4: 2b c0 rjmp .+86 ; 0x5c <__bad_interrupt> 6: 2a c0 rjmp .+84 ; 0x5c <__bad_interrupt> 8: 29 c0 rjmp .+82 ; 0x5c <__bad_interrupt> a: 28 c0 rjmp .+80 ; 0x5c <__bad_interrupt> c: 27 c0 rjmp .+78 ; 0x5c <__bad_interrupt> e: 26 c0 rjmp .+76 ; 0x5c <__bad_interrupt> 10: 25 c0 rjmp .+74 ; 0x5c <__bad_interrupt> 12: 5a c0 rjmp .+180 ; 0xc8 <__vector_9> 14: 23 c0 rjmp .+70 ; 0x5c <__bad_interrupt> 16: 22 c0 rjmp .+68 ; 0x5c <__bad_interrupt> 18: 21 c0 rjmp .+66 ; 0x5c <__bad_interrupt> 1a: 20 c0 rjmp .+64 ; 0x5c <__bad_interrupt> 1c: 1f c0 rjmp .+62 ; 0x5c <__bad_interrupt> 1e: 1e c0 rjmp .+60 ; 0x5c <__bad_interrupt> 20: 1d c0 rjmp .+58 ; 0x5c <__bad_interrupt> 22: 1c c0 rjmp .+56 ; 0x5c <__bad_interrupt> 24: 1b c0 rjmp .+54 ; 0x5c <__bad_interrupt> 00000026 <__ctors_end>: 26: 11 24 eor r1, r1 28: 1f be out 0x3f, r1 ; 63 2a: cf e5 ldi r28, 0x5F ; 95 2c: d4 e0 ldi r29, 0x04 ; 4 2e: de bf out 0x3e, r29 ; 62 30: cd bf out 0x3d, r28 ; 61 00000032 <__do_clear_bss>: 32: 10 e0 ldi r17, 0x00 ; 0 34: a4 e6 ldi r26, 0x64 ; 100 36: b0 e0 ldi r27, 0x00 ; 0 38: 01 c0 rjmp .+2 ; 0x3c <.do_clear_bss_start> 0000003a <.do_clear_bss_loop>: 3a: 1d 92 st X+, r1 0000003c <.do_clear_bss_start>: 3c: a3 3a cpi r26, 0xA3 ; 163 3e: b1 07 cpc r27, r17 40: e1 f7 brne .-8 ; 0x3a <.do_clear_bss_loop> 00000042 <__do_copy_data>: 42: 10 e0 ldi r17, 0x00 ; 0 44: a0 e6 ldi r26, 0x60 ; 96 46: b0 e0 ldi r27, 0x00 ; 0 48: e4 e4 ldi r30, 0x44 ; 68 4a: f5 e0 ldi r31, 0x05 ; 5 4c: 02 c0 rjmp .+4 ; 0x52 <.do_copy_data_start> 0000004e <.do_copy_data_loop>: 4e: 05 90 lpm r0, Z+ 50: 0d 92 st X+, r0 00000052 <.do_copy_data_start>: 52: a4 36 cpi r26, 0x64 ; 100 54: b1 07 cpc r27, r17 56: d9 f7 brne .-10 ; 0x4e <.do_copy_data_loop> 58: ad d0 rcall .+346 ; 0x1b4
5a: 72 c2 rjmp .+1252 ; 0x540 <_exit> 0000005c <__bad_interrupt>: 5c: d1 cf rjmp .-94 ; 0x0 <__vectors> 0000005e : void init() { // INITIALISIERUNG I/Os //DDRD |= (1< noch nicht verwendet 5e: 84 b3 in r24, 0x14 ; 20 60: 80 63 ori r24, 0x30 ; 48 62: 84 bb out 0x14, r24 ; 20 DDRB = 0xFF; // Output for speed LEDs, SRs and CLK control 64: 8f ef ldi r24, 0xFF ; 255 66: 87 bb out 0x17, r24 ; 23 // controller is SPI-"master" SPCR |= ((1< 4 MHz 6e: 70 9a sbi 0x0e, 0 ; 14 SPDR; 70: 8f b1 in r24, 0x0f ; 15 SPSR; 72: 8e b1 in r24, 0x0e ; 14 // INITIALISIERUNG UART UCSRA |= (1< 250k, 12 -> 76k8, 25 -> 38k4 7e: 8f ec ldi r24, 0xCF ; 207 80: 89 b9 out 0x09, r24 ; 9 // Initialisierung ADC //ADMUX |= ((1<: unsigned char zufallsgenerator(unsigned int tiefe) { 9c: bc 01 movw r22, r24 9e: 40 e0 ldi r20, 0x00 ; 0 a0: 20 e0 ldi r18, 0x00 ; 0 a2: 30 e0 ldi r19, 0x00 ; 0 a4: 0c c0 rjmp .+24 ; 0xbe unsigned char zahl = 0; for(unsigned int x = 0; x < tiefe; x++) { ADCSRA |= (1< while (ADCSRA & (1< { asm("NOP":); } zahl <<= 1; b0: 44 0f add r20, r20 zahl += (ADCW & 0x0001); b2: 84 b1 in r24, 0x04 ; 4 b4: 95 b1 in r25, 0x05 ; 5 b6: 81 70 andi r24, 0x01 ; 1 b8: 48 0f add r20, r24 unsigned char zufallsgenerator(unsigned int tiefe) { unsigned char zahl = 0; for(unsigned int x = 0; x < tiefe; x++) ba: 2f 5f subi r18, 0xFF ; 255 bc: 3f 4f sbci r19, 0xFF ; 255 be: 26 17 cp r18, r22 c0: 37 07 cpc r19, r23 c2: 88 f3 brcs .-30 ; 0xa6 zahl <<= 1; zahl += (ADCW & 0x0001); } return zahl; } c4: 84 2f mov r24, r20 c6: 08 95 ret 000000c8 <__vector_9>: ISR(TIMER0_OVF_vect) { c8: 1f 92 push r1 ca: 0f 92 push r0 cc: 0f b6 in r0, 0x3f ; 63 ce: 0f 92 push r0 d0: 11 24 eor r1, r1 d2: 2f 93 push r18 d4: 3f 93 push r19 d6: 4f 93 push r20 d8: 5f 93 push r21 da: 6f 93 push r22 dc: 7f 93 push r23 de: 8f 93 push r24 e0: 9f 93 push r25 e2: af 93 push r26 e4: bf 93 push r27 e6: ef 93 push r30 e8: ff 93 push r31 unsigned char temp = 0; unsigned char sr_nummer = 0; PORTB |= (1< pwm_max) ec: 80 91 64 00 lds r24, 0x0064 f0: 87 ff sbrs r24, 7 f2: 03 c0 rjmp .+6 ; 0xfa <__vector_9+0x32> { pwm_cycles = 0; f4: 10 92 64 00 sts 0x0064, r1 PORTB &= ~(1< 10e: 21 e0 ldi r18, 0x01 ; 1 if(pwm_cycles < helligkeit[sr_nummer + 1]) temp |= (1<<1); // <- wird dann "1, 9, 17, 25, 33, 41" 110: 90 91 64 00 lds r25, 0x0064 114: 81 81 ldd r24, Z+1 ; 0x01 116: 98 17 cp r25, r24 118: 08 f4 brcc .+2 ; 0x11c <__vector_9+0x54> 11a: 22 60 ori r18, 0x02 ; 2 if(pwm_cycles < helligkeit[sr_nummer + 2]) temp |= (1<<2); // <- wird dann "2, 10, 18, 26, 34, 42" 11c: 90 91 64 00 lds r25, 0x0064 120: 82 81 ldd r24, Z+2 ; 0x02 122: 98 17 cp r25, r24 124: 08 f4 brcc .+2 ; 0x128 <__vector_9+0x60> 126: 24 60 ori r18, 0x04 ; 4 if(pwm_cycles < helligkeit[sr_nummer + 3]) temp |= (1<<3); // <- wird dann "3, 11, 19, 27, 35, 43" 128: 90 91 64 00 lds r25, 0x0064 12c: 83 81 ldd r24, Z+3 ; 0x03 12e: 98 17 cp r25, r24 130: 08 f4 brcc .+2 ; 0x134 <__vector_9+0x6c> 132: 28 60 ori r18, 0x08 ; 8 if(pwm_cycles < helligkeit[sr_nummer + 4]) temp |= (1<<4); // <- wird dann "4, 12, 20, 28, 36, 44" 134: 90 91 64 00 lds r25, 0x0064 138: 84 81 ldd r24, Z+4 ; 0x04 13a: 98 17 cp r25, r24 13c: 08 f4 brcc .+2 ; 0x140 <__vector_9+0x78> 13e: 20 61 ori r18, 0x10 ; 16 if(pwm_cycles < helligkeit[sr_nummer + 5]) temp |= (1<<5); // <- wird dann "5, 13, 21, 29, 37, 45" 140: 90 91 64 00 lds r25, 0x0064 144: 85 81 ldd r24, Z+5 ; 0x05 146: 98 17 cp r25, r24 148: 08 f4 brcc .+2 ; 0x14c <__vector_9+0x84> 14a: 20 62 ori r18, 0x20 ; 32 if(pwm_cycles < helligkeit[sr_nummer + 6]) temp |= (1<<6); // <- wird dann "6, 14, 22, 30, 38, 46" 14c: 90 91 64 00 lds r25, 0x0064 150: 86 81 ldd r24, Z+6 ; 0x06 152: 98 17 cp r25, r24 154: 08 f4 brcc .+2 ; 0x158 <__vector_9+0x90> 156: 20 64 ori r18, 0x40 ; 64 if(pwm_cycles < helligkeit[sr_nummer + 7]) temp |= (1<<7); // <- wird dann "7, 15, 23, 31, 39, 47" 158: 90 91 64 00 lds r25, 0x0064 15c: 87 81 ldd r24, Z+7 ; 0x07 15e: 98 17 cp r25, r24 160: 08 f4 brcc .+2 ; 0x164 <__vector_9+0x9c> 162: 20 68 ori r18, 0x80 ; 128 schieberegister[count] = temp; 164: 2d 93 st X+, r18 166: 38 96 adiw r30, 0x08 ; 8 { schieberegister[(kanal>>3)] &= ~(1<<(kanal & 7)); // %8 } }*/ for(unsigned char count = 0; count < anzahl_schieberegister; count++) 168: 80 e0 ldi r24, 0x00 ; 0 16a: eb 38 cpi r30, 0x8B ; 139 16c: f8 07 cpc r31, r24 16e: 49 f6 brne .-110 ; 0x102 <__vector_9+0x3a> } for(signed char sr = (anzahl_schieberegister-1); sr >= 0; sr--) { transmit_8bit_spi(schieberegister[sr]); 170: 80 91 68 00 lds r24, 0x0068 174: 7d d0 rcall .+250 ; 0x270 176: 80 91 67 00 lds r24, 0x0067 17a: 7a d0 rcall .+244 ; 0x270 17c: 80 91 66 00 lds r24, 0x0066 180: 77 d0 rcall .+238 ; 0x270 //SPDR = (schieberegister[sr] ^ 0x0F); //while( !(SPSR & (1< pwm_cycles++; 184: 80 91 64 00 lds r24, 0x0064 188: 8f 5f subi r24, 0xFF ; 255 18a: 80 93 64 00 sts 0x0064, r24 TCNT0 = 193; 18e: 81 ec ldi r24, 0xC1 ; 193 190: 82 bf out 0x32, r24 ; 50 } 192: ff 91 pop r31 194: ef 91 pop r30 196: bf 91 pop r27 198: af 91 pop r26 19a: 9f 91 pop r25 19c: 8f 91 pop r24 19e: 7f 91 pop r23 1a0: 6f 91 pop r22 1a2: 5f 91 pop r21 1a4: 4f 91 pop r20 1a6: 3f 91 pop r19 1a8: 2f 91 pop r18 1aa: 0f 90 pop r0 1ac: 0f be out 0x3f, r0 ; 63 1ae: 0f 90 pop r0 1b0: 1f 90 pop r1 1b2: 18 95 reti 000001b4
: char line[10]; unsigned char zufallszahl; volatile unsigned char pwm_cycles = 0; int main() { 1b4: cf 93 push r28 1b6: df 93 push r29 //OSCCAL = 0xA5; OSCCAL = 0xFF; 1b8: 8f ef ldi r24, 0xFF ; 255 1ba: 81 bf out 0x31, r24 ; 49 init(); 1bc: 50 df rcall .-352 ; 0x5e clear_shift_registers(anzahl_schieberegister); 1be: 83 e0 ldi r24, 0x03 ; 3 1c0: 6c d0 rcall .+216 ; 0x29a zufallszahl = zufallsgenerator(50); 1c2: 82 e3 ldi r24, 0x32 ; 50 1c4: 90 e0 ldi r25, 0x00 ; 0 1c6: 6a df rcall .-300 ; 0x9c 1c8: 80 93 65 00 sts 0x0065, r24 srand(zufallszahl); 1cc: 90 e0 ldi r25, 0x00 ; 0 1ce: eb d0 rcall .+470 ; 0x3a6 1d0: c0 e0 ldi r28, 0x00 ; 0 1d2: d0 e0 ldi r29, 0x00 ; 0 // Laden der Startwerte und Werte für Blendgeschwindigkeit pro PWM-Kanal // Ausgabe via UART zum Überprüfen, Anzahl der ausgegebenen Werte = pwm_kanaele for(unsigned char kanal = 0; kanal < pwm_kanaele; kanal++) { speed[kanal] = rand() % (pwm_max + 1); 1d4: e4 d0 rcall .+456 ; 0x39e 1d6: fe 01 movw r30, r28 1d8: e5 57 subi r30, 0x75 ; 117 1da: ff 4f sbci r31, 0xFF ; 255 1dc: 60 e8 ldi r22, 0x80 ; 128 1de: 70 e0 ldi r23, 0x00 ; 0 1e0: 6d d0 rcall .+218 ; 0x2bc <__divmodhi4> 1e2: 80 83 st Z, r24 helligkeit[kanal] = rand() % (pwm_max + 1); 1e4: dc d0 rcall .+440 ; 0x39e 1e6: 60 e8 ldi r22, 0x80 ; 128 1e8: 70 e0 ldi r23, 0x00 ; 0 1ea: 68 d0 rcall .+208 ; 0x2bc <__divmodhi4> 1ec: fe 01 movw r30, r28 1ee: ed 58 subi r30, 0x8D ; 141 1f0: ff 4f sbci r31, 0xFF ; 255 1f2: 80 83 st Z, r24 itoa(helligkeit[kanal], line, 10); 1f4: 90 e0 ldi r25, 0x00 ; 0 1f6: 69 e6 ldi r22, 0x69 ; 105 1f8: 70 e0 ldi r23, 0x00 ; 0 1fa: 4a e0 ldi r20, 0x0A ; 10 1fc: 50 e0 ldi r21, 0x00 ; 0 1fe: de d0 rcall .+444 ; 0x3bc 200: 21 96 adiw r28, 0x01 ; 1 zufallszahl = zufallsgenerator(50); srand(zufallszahl); // Laden der Startwerte und Werte für Blendgeschwindigkeit pro PWM-Kanal // Ausgabe via UART zum Überprüfen, Anzahl der ausgegebenen Werte = pwm_kanaele for(unsigned char kanal = 0; kanal < pwm_kanaele; kanal++) 202: c8 31 cpi r28, 0x18 ; 24 204: d1 05 cpc r29, r1 206: 31 f7 brne .-52 ; 0x1d4 //uart_send_s(line); // <- muß auskommentiert werden?! //send_cursor_return; // <- muß auskommentiert werden?! //send_new_line; // <- muß auskommentiert werden?! } sei(); 208: 78 94 sei while(1) { asm("NOP":); 20a: 00 00 nop 20c: fe cf rjmp .-4 ; 0x20a 0000020e : #include "sternenhimmel.h" void uart_send_s(char *data) { 20e: fc 01 movw r30, r24 210: 04 c0 rjmp .+8 ; 0x21a } } void uart_send_c(unsigned char x) { while(!(UCSRA & (1 << UDRE))) 212: 5d 9b sbis 0x0b, 5 ; 11 214: fe cf rjmp .-4 ; 0x212 { ; // wait for UART to finish sending } UDR = x; 216: 8c b9 out 0x0c, r24 ; 12 void uart_send_s(char *data) { while(*data) { uart_send_c(*data); data++; 218: 31 96 adiw r30, 0x01 ; 1 #include "sternenhimmel.h" void uart_send_s(char *data) { while(*data) 21a: 80 81 ld r24, Z 21c: 88 23 and r24, r24 21e: c9 f7 brne .-14 ; 0x212 { uart_send_c(*data); data++; } } 220: 08 95 ret 00000222 : void uart_send_c(unsigned char x) { while(!(UCSRA & (1 << UDRE))) 222: 5d 9b sbis 0x0b, 5 ; 11 224: fe cf rjmp .-4 ; 0x222 { ; // wait for UART to finish sending } UDR = x; 226: 8c b9 out 0x0c, r24 ; 12 } 228: 08 95 ret 0000022a : void uart_get_s(char *buffer, unsigned char max_length) { 22a: 58 2f mov r21, r24 22c: 29 2f mov r18, r25 *buffer = '\0'; } unsigned char uart_get_c() { while(!(UCSRA & (1< { ; // wait for next character } return UDR; // return reveived character 232: 4c b1 in r20, 0x0c ; 12 234: 85 2f mov r24, r21 236: 92 2f mov r25, r18 238: 9c 01 movw r18, r24 23a: f9 01 movw r30, r18 next_char = uart_get_c(); // Warte auf und empfange das nächste Zeichen // Sammle solange Zeichen, bis: // * entweder das String-Ende-Zeichen kam // * oder das aufnehmende Array voll ist while( (next_char != 0x0D) && (string_length < (max_length - 1)) ) 23c: 70 e0 ldi r23, 0x00 ; 0 23e: 61 50 subi r22, 0x01 ; 1 240: 70 40 sbci r23, 0x00 ; 0 242: 08 c0 rjmp .+16 ; 0x254 { *buffer++ = next_char; 244: 40 83 st Z, r20 } } void uart_send_c(unsigned char x) { while(!(UCSRA & (1 << UDRE))) 246: 5d 9b sbis 0x0b, 5 ; 11 248: fe cf rjmp .-4 ; 0x246 { ; // wait for UART to finish sending } UDR = x; 24a: 4c b9 out 0x0c, r20 ; 12 *buffer = '\0'; } unsigned char uart_get_c() { while(!(UCSRA & (1< // Sammle solange Zeichen, bis: // * entweder das String-Ende-Zeichen kam // * oder das aufnehmende Array voll ist while( (next_char != 0x0D) && (string_length < (max_length - 1)) ) { *buffer++ = next_char; 250: 31 96 adiw r30, 0x01 ; 1 while(!(UCSRA & (1< 25c: 90 e0 ldi r25, 0x00 ; 0 25e: 86 17 cp r24, r22 260: 97 07 cpc r25, r23 262: 84 f3 brlt .-32 ; 0x244 next_char = uart_get_c(); } // Noch ein '\0' anhängen um einen Standard // C-String daraus zu machen *buffer = '\0'; 264: 10 82 st Z, r1 } 266: 08 95 ret 00000268 : unsigned char uart_get_c() { while(!(UCSRA & (1< { ; // wait for next character } return UDR; // return reveived character 26c: 8c b1 in r24, 0x0c ; 12 } 26e: 08 95 ret 00000270 : void transmit_8bit_spi(unsigned char data) { //enable_spi; SPDR = (data ^ 0x0F); 270: 9f e0 ldi r25, 0x0F ; 15 272: 98 27 eor r25, r24 274: 9f b9 out 0x0f, r25 ; 15 //SPDR = data; // wait for transmission to be finished while( !(SPSR & (1< // clear flag by reading SPDR; 27a: 8f b1 in r24, 0x0f ; 15 //disable_spi; //PORTB &= ~(1<: void transmit_16bit_spi(unsigned int data) { 27e: 28 2f mov r18, r24 void transmit_8bit_spi(unsigned char data) { //enable_spi; SPDR = (data ^ 0x0F); 280: 8f e0 ldi r24, 0x0F ; 15 282: 89 27 eor r24, r25 284: 8f b9 out 0x0f, r24 ; 15 //SPDR = data; // wait for transmission to be finished while( !(SPSR & (1< // clear flag by reading SPDR; 28a: 8f b1 in r24, 0x0f ; 15 void transmit_8bit_spi(unsigned char data) { //enable_spi; SPDR = (data ^ 0x0F); 28c: 8f e0 ldi r24, 0x0F ; 15 28e: 82 27 eor r24, r18 290: 8f b9 out 0x0f, r24 ; 15 //SPDR = data; // wait for transmission to be finished while( !(SPSR & (1< // clear flag by reading SPDR; 296: 8f b1 in r24, 0x0f ; 15 // transmit higher byte of 16-bit-int transmit_8bit_spi(data >> 8); // transmit lower byte of 16-bit-int transmit_8bit_spi(data & 0xFF); } 298: 08 95 ret 0000029a : void transmit_8bit_spi(unsigned char data) { //enable_spi; SPDR = (data ^ 0x0F); 29a: 9f e0 ldi r25, 0x0F ; 15 29c: 05 c0 rjmp .+10 ; 0x2a8 29e: 9f b9 out 0x0f, r25 ; 15 //SPDR = data; // wait for transmission to be finished while( !(SPSR & (1< // clear flag by reading SPDR; 2a4: 2f b1 in r18, 0x0f ; 15 } void clear_shift_registers(signed char count) { for(;count > 0; count--) 2a6: 81 50 subi r24, 0x01 ; 1 2a8: 18 16 cp r1, r24 2aa: cc f3 brlt .-14 ; 0x29e } void output_sr_latch() { PORTB &= ~(1<: void output_sr_latch() { PORTB &= ~(1<: 2bc: 97 fb bst r25, 7 2be: 09 2e mov r0, r25 2c0: 07 26 eor r0, r23 2c2: 0a d0 rcall .+20 ; 0x2d8 <__divmodhi4_neg1> 2c4: 77 fd sbrc r23, 7 2c6: 04 d0 rcall .+8 ; 0x2d0 <__divmodhi4_neg2> 2c8: 0c d0 rcall .+24 ; 0x2e2 <__udivmodhi4> 2ca: 06 d0 rcall .+12 ; 0x2d8 <__divmodhi4_neg1> 2cc: 00 20 and r0, r0 2ce: 1a f4 brpl .+6 ; 0x2d6 <__divmodhi4_exit> 000002d0 <__divmodhi4_neg2>: 2d0: 70 95 com r23 2d2: 61 95 neg r22 2d4: 7f 4f sbci r23, 0xFF ; 255 000002d6 <__divmodhi4_exit>: 2d6: 08 95 ret 000002d8 <__divmodhi4_neg1>: 2d8: f6 f7 brtc .-4 ; 0x2d6 <__divmodhi4_exit> 2da: 90 95 com r25 2dc: 81 95 neg r24 2de: 9f 4f sbci r25, 0xFF ; 255 2e0: 08 95 ret 000002e2 <__udivmodhi4>: 2e2: aa 1b sub r26, r26 2e4: bb 1b sub r27, r27 2e6: 51 e1 ldi r21, 0x11 ; 17 2e8: 07 c0 rjmp .+14 ; 0x2f8 <__udivmodhi4_ep> 000002ea <__udivmodhi4_loop>: 2ea: aa 1f adc r26, r26 2ec: bb 1f adc r27, r27 2ee: a6 17 cp r26, r22 2f0: b7 07 cpc r27, r23 2f2: 10 f0 brcs .+4 ; 0x2f8 <__udivmodhi4_ep> 2f4: a6 1b sub r26, r22 2f6: b7 0b sbc r27, r23 000002f8 <__udivmodhi4_ep>: 2f8: 88 1f adc r24, r24 2fa: 99 1f adc r25, r25 2fc: 5a 95 dec r21 2fe: a9 f7 brne .-22 ; 0x2ea <__udivmodhi4_loop> 300: 80 95 com r24 302: 90 95 com r25 304: bc 01 movw r22, r24 306: cd 01 movw r24, r26 308: 08 95 ret 0000030a : 30a: a0 e0 ldi r26, 0x00 ; 0 30c: b0 e0 ldi r27, 0x00 ; 0 30e: ea e8 ldi r30, 0x8A ; 138 310: f1 e0 ldi r31, 0x01 ; 1 312: c5 c0 rjmp .+394 ; 0x49e <__prologue_saves__+0x10> 314: ec 01 movw r28, r24 316: a8 80 ld r10, Y 318: b9 80 ldd r11, Y+1 ; 0x01 31a: ca 80 ldd r12, Y+2 ; 0x02 31c: db 80 ldd r13, Y+3 ; 0x03 31e: a1 14 cp r10, r1 320: b1 04 cpc r11, r1 322: c1 04 cpc r12, r1 324: d1 04 cpc r13, r1 326: 41 f4 brne .+16 ; 0x338 328: 84 e2 ldi r24, 0x24 ; 36 32a: a8 2e mov r10, r24 32c: 89 ed ldi r24, 0xD9 ; 217 32e: b8 2e mov r11, r24 330: 8b e5 ldi r24, 0x5B ; 91 332: c8 2e mov r12, r24 334: 87 e0 ldi r24, 0x07 ; 7 336: d8 2e mov r13, r24 338: c6 01 movw r24, r12 33a: b5 01 movw r22, r10 33c: 2d e1 ldi r18, 0x1D ; 29 33e: 33 ef ldi r19, 0xF3 ; 243 340: 41 e0 ldi r20, 0x01 ; 1 342: 50 e0 ldi r21, 0x00 ; 0 344: 89 d0 rcall .+274 ; 0x458 <__divmodsi4> 346: 27 ea ldi r18, 0xA7 ; 167 348: 31 e4 ldi r19, 0x41 ; 65 34a: 40 e0 ldi r20, 0x00 ; 0 34c: 50 e0 ldi r21, 0x00 ; 0 34e: 65 d0 rcall .+202 ; 0x41a <__mulsi3> 350: 7b 01 movw r14, r22 352: 8c 01 movw r16, r24 354: c6 01 movw r24, r12 356: b5 01 movw r22, r10 358: 2d e1 ldi r18, 0x1D ; 29 35a: 33 ef ldi r19, 0xF3 ; 243 35c: 41 e0 ldi r20, 0x01 ; 1 35e: 50 e0 ldi r21, 0x00 ; 0 360: 7b d0 rcall .+246 ; 0x458 <__divmodsi4> 362: ca 01 movw r24, r20 364: b9 01 movw r22, r18 366: 2c ee ldi r18, 0xEC ; 236 368: 34 ef ldi r19, 0xF4 ; 244 36a: 4f ef ldi r20, 0xFF ; 255 36c: 5f ef ldi r21, 0xFF ; 255 36e: 55 d0 rcall .+170 ; 0x41a <__mulsi3> 370: 6e 0d add r22, r14 372: 7f 1d adc r23, r15 374: 80 1f adc r24, r16 376: 91 1f adc r25, r17 378: 97 ff sbrs r25, 7 37a: 04 c0 rjmp .+8 ; 0x384 37c: 61 50 subi r22, 0x01 ; 1 37e: 70 40 sbci r23, 0x00 ; 0 380: 80 40 sbci r24, 0x00 ; 0 382: 90 48 sbci r25, 0x80 ; 128 384: 68 83 st Y, r22 386: 79 83 std Y+1, r23 ; 0x01 388: 8a 83 std Y+2, r24 ; 0x02 38a: 9b 83 std Y+3, r25 ; 0x03 38c: 9b 01 movw r18, r22 38e: 3f 77 andi r19, 0x7F ; 127 390: c9 01 movw r24, r18 392: cd b7 in r28, 0x3d ; 61 394: de b7 in r29, 0x3e ; 62 396: ea e0 ldi r30, 0x0A ; 10 398: 9e c0 rjmp .+316 ; 0x4d6 <__epilogue_restores__+0x10> 0000039a : 39a: b7 df rcall .-146 ; 0x30a 39c: 08 95 ret 0000039e : 39e: 80 e6 ldi r24, 0x60 ; 96 3a0: 90 e0 ldi r25, 0x00 ; 0 3a2: b3 df rcall .-154 ; 0x30a 3a4: 08 95 ret 000003a6 : 3a6: a0 e0 ldi r26, 0x00 ; 0 3a8: b0 e0 ldi r27, 0x00 ; 0 3aa: 80 93 60 00 sts 0x0060, r24 3ae: 90 93 61 00 sts 0x0061, r25 3b2: a0 93 62 00 sts 0x0062, r26 3b6: b0 93 63 00 sts 0x0063, r27 3ba: 08 95 ret 000003bc : 3bc: fb 01 movw r30, r22 3be: 9f 01 movw r18, r30 3c0: e8 94 clt 3c2: 42 30 cpi r20, 0x02 ; 2 3c4: bc f0 brlt .+46 ; 0x3f4 3c6: 45 32 cpi r20, 0x25 ; 37 3c8: ac f4 brge .+42 ; 0x3f4 3ca: 4a 30 cpi r20, 0x0A ; 10 3cc: 29 f4 brne .+10 ; 0x3d8 3ce: 97 fb bst r25, 7 3d0: 1e f4 brtc .+6 ; 0x3d8 3d2: 90 95 com r25 3d4: 81 95 neg r24 3d6: 9f 4f sbci r25, 0xFF ; 255 3d8: 64 2f mov r22, r20 3da: 77 27 eor r23, r23 3dc: 82 df rcall .-252 ; 0x2e2 <__udivmodhi4> 3de: 80 5d subi r24, 0xD0 ; 208 3e0: 8a 33 cpi r24, 0x3A ; 58 3e2: 0c f0 brlt .+2 ; 0x3e6 3e4: 89 5d subi r24, 0xD9 ; 217 3e6: 81 93 st Z+, r24 3e8: cb 01 movw r24, r22 3ea: 00 97 sbiw r24, 0x00 ; 0 3ec: a9 f7 brne .-22 ; 0x3d8 3ee: 16 f4 brtc .+4 ; 0x3f4 3f0: 5d e2 ldi r21, 0x2D ; 45 3f2: 51 93 st Z+, r21 3f4: 10 82 st Z, r1 3f6: c9 01 movw r24, r18 3f8: 00 c0 rjmp .+0 ; 0x3fa 000003fa : 3fa: dc 01 movw r26, r24 3fc: fc 01 movw r30, r24 3fe: 67 2f mov r22, r23 400: 71 91 ld r23, Z+ 402: 77 23 and r23, r23 404: e1 f7 brne .-8 ; 0x3fe 406: 32 97 sbiw r30, 0x02 ; 2 408: 04 c0 rjmp .+8 ; 0x412 40a: 7c 91 ld r23, X 40c: 6d 93 st X+, r22 40e: 70 83 st Z, r23 410: 62 91 ld r22, -Z 412: ae 17 cp r26, r30 414: bf 07 cpc r27, r31 416: c8 f3 brcs .-14 ; 0x40a 418: 08 95 ret 0000041a <__mulsi3>: 41a: 62 9f mul r22, r18 41c: d0 01 movw r26, r0 41e: 73 9f mul r23, r19 420: f0 01 movw r30, r0 422: 82 9f mul r24, r18 424: e0 0d add r30, r0 426: f1 1d adc r31, r1 428: 64 9f mul r22, r20 42a: e0 0d add r30, r0 42c: f1 1d adc r31, r1 42e: 92 9f mul r25, r18 430: f0 0d add r31, r0 432: 83 9f mul r24, r19 434: f0 0d add r31, r0 436: 74 9f mul r23, r20 438: f0 0d add r31, r0 43a: 65 9f mul r22, r21 43c: f0 0d add r31, r0 43e: 99 27 eor r25, r25 440: 72 9f mul r23, r18 442: b0 0d add r27, r0 444: e1 1d adc r30, r1 446: f9 1f adc r31, r25 448: 63 9f mul r22, r19 44a: b0 0d add r27, r0 44c: e1 1d adc r30, r1 44e: f9 1f adc r31, r25 450: bd 01 movw r22, r26 452: cf 01 movw r24, r30 454: 11 24 eor r1, r1 456: 08 95 ret 00000458 <__divmodsi4>: 458: 97 fb bst r25, 7 45a: 09 2e mov r0, r25 45c: 05 26 eor r0, r21 45e: 0e d0 rcall .+28 ; 0x47c <__divmodsi4_neg1> 460: 57 fd sbrc r21, 7 462: 04 d0 rcall .+8 ; 0x46c <__divmodsi4_neg2> 464: 4b d0 rcall .+150 ; 0x4fc <__udivmodsi4> 466: 0a d0 rcall .+20 ; 0x47c <__divmodsi4_neg1> 468: 00 1c adc r0, r0 46a: 38 f4 brcc .+14 ; 0x47a <__divmodsi4_exit> 0000046c <__divmodsi4_neg2>: 46c: 50 95 com r21 46e: 40 95 com r20 470: 30 95 com r19 472: 21 95 neg r18 474: 3f 4f sbci r19, 0xFF ; 255 476: 4f 4f sbci r20, 0xFF ; 255 478: 5f 4f sbci r21, 0xFF ; 255 0000047a <__divmodsi4_exit>: 47a: 08 95 ret 0000047c <__divmodsi4_neg1>: 47c: f6 f7 brtc .-4 ; 0x47a <__divmodsi4_exit> 47e: 90 95 com r25 480: 80 95 com r24 482: 70 95 com r23 484: 61 95 neg r22 486: 7f 4f sbci r23, 0xFF ; 255 488: 8f 4f sbci r24, 0xFF ; 255 48a: 9f 4f sbci r25, 0xFF ; 255 48c: 08 95 ret 0000048e <__prologue_saves__>: 48e: 2f 92 push r2 490: 3f 92 push r3 492: 4f 92 push r4 494: 5f 92 push r5 496: 6f 92 push r6 498: 7f 92 push r7 49a: 8f 92 push r8 49c: 9f 92 push r9 49e: af 92 push r10 4a0: bf 92 push r11 4a2: cf 92 push r12 4a4: df 92 push r13 4a6: ef 92 push r14 4a8: ff 92 push r15 4aa: 0f 93 push r16 4ac: 1f 93 push r17 4ae: cf 93 push r28 4b0: df 93 push r29 4b2: cd b7 in r28, 0x3d ; 61 4b4: de b7 in r29, 0x3e ; 62 4b6: ca 1b sub r28, r26 4b8: db 0b sbc r29, r27 4ba: 0f b6 in r0, 0x3f ; 63 4bc: f8 94 cli 4be: de bf out 0x3e, r29 ; 62 4c0: 0f be out 0x3f, r0 ; 63 4c2: cd bf out 0x3d, r28 ; 61 4c4: 09 94 ijmp 000004c6 <__epilogue_restores__>: 4c6: 2a 88 ldd r2, Y+18 ; 0x12 4c8: 39 88 ldd r3, Y+17 ; 0x11 4ca: 48 88 ldd r4, Y+16 ; 0x10 4cc: 5f 84 ldd r5, Y+15 ; 0x0f 4ce: 6e 84 ldd r6, Y+14 ; 0x0e 4d0: 7d 84 ldd r7, Y+13 ; 0x0d 4d2: 8c 84 ldd r8, Y+12 ; 0x0c 4d4: 9b 84 ldd r9, Y+11 ; 0x0b 4d6: aa 84 ldd r10, Y+10 ; 0x0a 4d8: b9 84 ldd r11, Y+9 ; 0x09 4da: c8 84 ldd r12, Y+8 ; 0x08 4dc: df 80 ldd r13, Y+7 ; 0x07 4de: ee 80 ldd r14, Y+6 ; 0x06 4e0: fd 80 ldd r15, Y+5 ; 0x05 4e2: 0c 81 ldd r16, Y+4 ; 0x04 4e4: 1b 81 ldd r17, Y+3 ; 0x03 4e6: aa 81 ldd r26, Y+2 ; 0x02 4e8: b9 81 ldd r27, Y+1 ; 0x01 4ea: ce 0f add r28, r30 4ec: d1 1d adc r29, r1 4ee: 0f b6 in r0, 0x3f ; 63 4f0: f8 94 cli 4f2: de bf out 0x3e, r29 ; 62 4f4: 0f be out 0x3f, r0 ; 63 4f6: cd bf out 0x3d, r28 ; 61 4f8: ed 01 movw r28, r26 4fa: 08 95 ret 000004fc <__udivmodsi4>: 4fc: a1 e2 ldi r26, 0x21 ; 33 4fe: 1a 2e mov r1, r26 500: aa 1b sub r26, r26 502: bb 1b sub r27, r27 504: fd 01 movw r30, r26 506: 0d c0 rjmp .+26 ; 0x522 <__udivmodsi4_ep> 00000508 <__udivmodsi4_loop>: 508: aa 1f adc r26, r26 50a: bb 1f adc r27, r27 50c: ee 1f adc r30, r30 50e: ff 1f adc r31, r31 510: a2 17 cp r26, r18 512: b3 07 cpc r27, r19 514: e4 07 cpc r30, r20 516: f5 07 cpc r31, r21 518: 20 f0 brcs .+8 ; 0x522 <__udivmodsi4_ep> 51a: a2 1b sub r26, r18 51c: b3 0b sbc r27, r19 51e: e4 0b sbc r30, r20 520: f5 0b sbc r31, r21 00000522 <__udivmodsi4_ep>: 522: 66 1f adc r22, r22 524: 77 1f adc r23, r23 526: 88 1f adc r24, r24 528: 99 1f adc r25, r25 52a: 1a 94 dec r1 52c: 69 f7 brne .-38 ; 0x508 <__udivmodsi4_loop> 52e: 60 95 com r22 530: 70 95 com r23 532: 80 95 com r24 534: 90 95 com r25 536: 9b 01 movw r18, r22 538: ac 01 movw r20, r24 53a: bd 01 movw r22, r26 53c: cf 01 movw r24, r30 53e: 08 95 ret 00000540 <_exit>: 540: f8 94 cli 00000542 <__stop_program>: 542: ff cf rjmp .-2 ; 0x542 <__stop_program>