library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity blinklicht is Port ( clk : in STD_LOGIC; led : out STD_LOGIC); end blinklicht; architecture Behavioral of blinklicht is SIGNAL counter : STD_LOGIC_VECTOR (21 downto 0); begin timer: PROCESS (clk) BEGIN IF RISING_EDGE(clk) THEN counter <= counter + '1'; END IF; END PROCESS timer; led <= counter(21); end Behavioral;