Reading design: berechnen.prj

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/Praktikum_GSSE/9_Beleg/xilinx/222/konstanten.vhd" in Library work.
Entity <konstanten> compiled.
Entity <konstanten> (Architecture <behav>) compiled.
Compiling vhdl file "D:/Praktikum_GSSE/9_Beleg/xilinx/222/bedienung.vhd" in Library work.
Entity <bedienung> compiled.
Entity <bedienung> (Architecture <behav>) compiled.
Compiling vhdl file "D:/Praktikum_GSSE/9_Beleg/xilinx/222/Eingang.vhd" in Library work.
Entity <Eingang> compiled.
Entity <Eingang> (Architecture <behav>) compiled.
Compiling vhdl file "D:/Praktikum_GSSE/9_Beleg/xilinx/222/multipli.vhd" in Library work.
Entity <multipli> compiled.
Entity <multipli> (Architecture <behav>) compiled.
Compiling vhdl file "D:/Praktikum_GSSE/9_Beleg/xilinx/222/Takteingang.vhd" in Library work.
Entity <Takteingang> compiled.
Entity <Takteingang> (Architecture <behav>) compiled.
Compiling vhdl file "D:/Praktikum_GSSE/9_Beleg/xilinx/222/dividi.vhd" in Library work.
Entity <dividi> compiled.
Entity <dividi> (Architecture <behav>) compiled.
Compiling vhdl file "D:/Praktikum_GSSE/9_Beleg/xilinx/222/multi_cod.vhd" in Library work.
Entity <multi_cod> compiled.
Entity <multi_cod> (Architecture <behav>) compiled.
Compiling vhdl file "D:/Praktikum_GSSE/9_Beleg/xilinx/222/berechnung.vhd" in Library work.
Entity <berechnen> compiled.
Entity <berechnen> (Architecture <blockschaltung>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <berechnen> in library <work> (architecture <blockschaltung>).

Analyzing hierarchy for entity <konstanten> in library <work> (architecture <behav>).

Analyzing hierarchy for entity <bedienung> in library <work> (architecture <behav>).

Analyzing hierarchy for entity <Eingang> in library <work> (architecture <behav>).

Analyzing hierarchy for entity <multipli> in library <work> (architecture <behav>).

Analyzing hierarchy for entity <Takteingang> in library <work> (architecture <behav>).

Analyzing hierarchy for entity <dividi> in library <work> (architecture <behav>).

Analyzing hierarchy for entity <multi_cod> in library <work> (architecture <behav>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <berechnen> in library <work> (Architecture <blockschaltung>).
Entity <berechnen> analyzed. Unit <berechnen> generated.

Analyzing Entity <konstanten> in library <work> (Architecture <behav>).
Entity <konstanten> analyzed. Unit <konstanten> generated.

Analyzing Entity <bedienung> in library <work> (Architecture <behav>).
Entity <bedienung> analyzed. Unit <bedienung> generated.

Analyzing Entity <Eingang> in library <work> (Architecture <behav>).
Entity <Eingang> analyzed. Unit <Eingang> generated.

Analyzing Entity <multipli> in library <work> (Architecture <behav>).
Entity <multipli> analyzed. Unit <multipli> generated.

Analyzing Entity <Takteingang> in library <work> (Architecture <behav>).
Entity <Takteingang> analyzed. Unit <Takteingang> generated.

Analyzing Entity <dividi> in library <work> (Architecture <behav>).
ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict.  Current memory usage is 2089816 kb.  You can try increasing your system's physical or virtual memory.  For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. 

Process "Synthesis" failed