test.vhd

--------------------------------------------------------------------------------

-- Company: 

-- Engineer:

--

-- Create Date:   21:56:48 05/01/2011

-- Design Name:   

-- Module Name:   I:/ISE_Projekte/Ampelsteuerung/test.vhd

-- Project Name:  Ampelsteuerung

-- Target Device:  

-- Tool versions:  

-- Description:   

-- 

-- VHDL Test Bench Created by ISE for module: Main

-- 

-- Dependencies:

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes: 

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test.  Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation 

-- simulation model.

--------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY test IS

END test;

ARCHITECTURE behavior OF test IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Main

    PORT(

         CLK : IN  bit;

         RESET : IN  bit;

         HS1 : IN  bit;

         HS2 : IN  bit;

         NS1 : IN  bit;

         NS2 : IN  bit;

         FH : IN  bit;

         FN : IN  bit;

         BLINK : IN  bit;

         GRH : OUT  bit;

         GEH : OUT  bit;

         RH : OUT  bit;

         GRN : OUT  bit;

         GEN : OUT  bit;

         RN : OUT  bit;

         GFH : OUT  bit;

         RFH : OUT  bit;

         GFN : OUT  bit;

         RFN : OUT  bit;

         CNT_OUT : OUT  std_logic_vector(4 downto 0);

         ANZEIGE : OUT  bit_vector(3 downto 0)

        );

    END COMPONENT;

   --Inputs

   signal CLK : bit := '0';

   signal RESET : bit := '0';

   signal HS1 : bit := '0';

   signal HS2 : bit := '0';

   signal NS1 : bit := '0';

   signal NS2 : bit := '0';

   signal FH : bit := '0';

   signal FN : bit := '0';

   signal BLINK : bit := '0';

   --Outputs

   signal GRH : bit;

   signal GEH : bit;

   signal RH : bit;

   signal GRN : bit;

   signal GEN : bit;

   signal RN : bit;

   signal GFH : bit;

   signal RFH : bit;

   signal GFN : bit;

   signal RFN : bit;

   signal CNT_OUT : std_logic_vector(4 downto 0);

   signal ANZEIGE : bit_vector(3 downto 0);

   -- Clock period definitions

   constant CLK_period : time := 10 ns;

BEGIN

  -- Instantiate the Unit Under Test (UUT)

   uut: Main PORT MAP (

          CLK => CLK,

          RESET => RESET,

          HS1 => HS1,

          HS2 => HS2,

          NS1 => NS1,

          NS2 => NS2,

          FH => FH,

          FN => FN,

          BLINK => BLINK,

          GRH => GRH,

          GEH => GEH,

          RH => RH,

          GRN => GRN,

          GEN => GEN,

          RN => RN,

          GFH => GFH,

          RFH => RFH,

          GFN => GFN,

          RFN => RFN,

          CNT_OUT => CNT_OUT,

          ANZEIGE => ANZEIGE

        );

   -- Clock process definitions

   CLK_process :process

   begin

    CLK <= '0';

    wait for CLK_period/2;

    CLK <= '1';

    wait for CLK_period/2;

   end process;

   -- Stimulus process

   stim_proc: process

   begin    

      -- hold reset state for 100 ns.

      wait for 100 ns;  

      wait for CLK_period*10;

      -- insert stimulus here 

    RESET <= '0', '1' after 20 ms, '0' after 100 ms;

    --BLINK <= '0', '1' after 20 ms, '0' after 20000 ms;

      wait;

   end process;

END;