1 | #include <avr/io.h>
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2 | #include <avr/interrupt.h>
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3 |
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4 | #define USI_DATA USIDR
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5 | #define USI_STATUS USISR
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6 | #define USI_CONTROL USICR
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7 | #define USI_ADDRESS 0x08
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8 |
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9 | #define NONE 0
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10 | #define ACK_PR_RX 1
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11 | #define BYTE_RX 2
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12 | #define ACK_PR_TX 3
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13 | #define PR_ACK_TX 4
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14 | #define BYTE_TX 5
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15 |
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16 | #define DDR_USI DDRA
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17 | #define PORT_USI PORTA
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18 | #define PIN_USI PINA
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19 | #define PORT_USI_SDA PORTA6
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20 | #define PORT_USI_SCL PORTA4
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21 |
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22 | #define RC_OFFSET 100
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23 |
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24 | volatile uint8_t COMM_STATUS = NONE;
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25 | volatile uint8_t ACT_CHANNEL = NONE;
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26 | volatile uint8_t tWidth_1=0, tWidth_2=0, tWidth_3=0, tWidth_4=0;
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27 |
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28 | uint8_t tStart_1=0, tStart_2=0, tStart_3=0, tStart_4=0;
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29 |
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30 |
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31 | void USIinit(void) {
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32 | // 2-wire mode; Hold SCL on start and overflow; ext. clock
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33 | USI_CONTROL |= (1<<USIWM1) | (1<<USICS1);
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34 | USI_STATUS = 0xf0; // write 1 to clear flags, clear counter
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35 | DDR_USI &= ~(1<<PORT_USI_SDA);
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36 | PORT_USI &= ~(1<<PORT_USI_SDA);
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37 | DDR_USI |= (1<<PORT_USI_SCL);
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38 | PORT_USI |= (1<<PORT_USI_SCL);
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39 | // startcondition interrupt enable
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40 | USI_CONTROL |= (1<<USISIE);
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41 | }
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42 |
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43 | void RCinit(void) {
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44 | TCCR0B |= (1<<CS00) | (1<<CS01); //Prescaler
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45 | PCMSK0 |= (1<<PCINT0) | (1<<PCINT1) | (1<<PCINT2) | (1<<PCINT3); //PC Maske
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46 | GIMSK |= (1<<PCIE0);//Interrupt anschalten
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47 |
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48 | DDRB &= ~ (1<<DDB0) | (1<<DDB1) | (1<<DDB2) | (1<<DDB3); //Port A auf Eingang
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49 | PORTB &= ~ (1<<PORTB0) | (1<<PORTB1) | (1<<PORTB2) | (1<<PORTB3); //PullUp ausschalten
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50 | }
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51 |
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52 |
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53 | int main(void) {
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54 | RCinit();
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55 | USIinit();
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56 |
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57 | sei();
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58 |
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59 | for(;;) {
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60 | }
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61 |
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62 | }
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63 |
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64 |
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65 | ISR (USI_STR_vect) {
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66 | uint8_t tmpUSI_STATUS;
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67 | tmpUSI_STATUS = USI_STATUS;
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68 | COMM_STATUS = NONE;
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69 | // Wait for SCL to go low to ensure the "Start Condition" has completed.
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70 | // otherwise the counter will count the transition
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71 | while ( (PIN_USI & (1<<PORT_USI_SCL)) );
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72 | USI_STATUS = 0xf0; // write 1 to clear flags; clear counter
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73 | // enable USI interrupt on overflow; SCL goes low on overflow
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74 | USI_CONTROL |= (1<<USIOIE) | (1<<USIWM0);
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75 | }
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76 |
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77 |
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78 |
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79 |
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80 | ISR (USI_OVF_vect) {
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81 | uint8_t BUF_USI_DATA = USI_DATA;
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82 | switch(COMM_STATUS) {
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83 | case NONE:
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84 | if (((BUF_USI_DATA & 0xfe) >> 1) != USI_ADDRESS) { // if not receiving my address
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85 | // disable USI interrupt on overflow; disable SCL low on overflow
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86 | USI_CONTROL &= ~((1<<USIOIE) | (1<<USIWM0));
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87 | }
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88 | else { // else address is mine
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89 | DDR_USI |= (1<<PORT_USI_SDA);
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90 | USI_STATUS = 0x0e; // reload counter for ACK, (SCL) high and back low
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91 | if (BUF_USI_DATA & 0x01) {
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92 | COMM_STATUS = ACK_PR_TX;
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93 | } else {
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94 | COMM_STATUS = ACK_PR_RX;
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95 | }
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96 | }
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97 | break;
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98 | case ACK_PR_RX:
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99 | DDR_USI &= ~(1<<PORT_USI_SDA);
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100 | COMM_STATUS = BYTE_RX;
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101 | break;
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102 | case BYTE_RX:
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103 | ACT_CHANNEL = USI_DATA; //Empfangenes Byte als aktuellen Channel speichern
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104 | DDR_USI |= (1<<PORT_USI_SDA);
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105 | USI_STATUS = 0x0e; // reload counter for ACK, (SCL) high and back low
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106 | COMM_STATUS = ACK_PR_RX;
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107 | break;
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108 | case ACK_PR_TX:
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109 | //Aktuellen kanal senden
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110 | switch (ACT_CHANNEL) {
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111 | case 1:
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112 | USI_DATA = tWidth_1;
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113 | break;
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114 | case 2:
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115 | USI_DATA = tWidth_2;
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116 | break;
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117 | case 3:
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118 | USI_DATA = tWidth_3;
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119 | break;
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120 | case 4:
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121 | USI_DATA = tWidth_4;
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122 | break;
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123 | }
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124 | PORT_USI |= (1<<PORT_USI_SDA); // transparent for shifting data out
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125 | COMM_STATUS = BYTE_TX;
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126 | break;
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127 | case PR_ACK_TX:
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128 | if(BUF_USI_DATA & 0x01) {
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129 | COMM_STATUS = NONE; // no ACK from master --> no more bytes to send
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130 | }
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131 | else {
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132 | /* Put next byte to transmit in buffer here! USI_DATA = ... */
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133 | PORT_USI |= (1<<PORT_USI_SDA); // transparent for shifting data out
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134 | DDR_USI |= (1<<PORT_USI_SDA);
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135 | COMM_STATUS = BYTE_TX;
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136 | }
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137 | break;
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138 | case BYTE_TX:
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139 | DDR_USI &= ~(1<<PORT_USI_SDA);
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140 | PORT_USI &= ~(1<<PORT_USI_SDA);
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141 | USI_STATUS = 0x0e; // reload counter for ACK, (SCL) high and back low
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142 | COMM_STATUS = PR_ACK_TX;
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143 | break;
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144 | }
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145 | USI_STATUS |= (1<<USIOIF); // clear overflowinterruptflag, this also releases SCL
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146 | }
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147 |
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148 |
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149 | ISR(PCINT0_vect) {
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150 | //Channel 1
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151 | if (PINB & ( 1 << PINB0 ))
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152 | {
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153 | tStart_1 = TCNT0;
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154 | }
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155 | if (!(PINB & ( 1 << PINB0 )) && (tStart_1!=0))
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156 | {
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157 | tWidth_1 = TCNT0 - tStart_1 - RC_OFFSET;
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158 | tStart_1 = 0;
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159 | }
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160 |
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161 | //Channel 2
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162 | if (PINB & ( 1 << PINB1 ))
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163 | {
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164 | tStart_2 = TCNT0;
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165 | }
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166 | if (!(PINB & ( 1 << PINB1 )) && (tStart_2!=0))
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167 | {
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168 | tWidth_2 = TCNT0 - tStart_2 - RC_OFFSET;
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169 | tStart_2 = 0;
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170 | }
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171 |
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172 | //Channel 3
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173 | if (PINB & ( 1 << PINB2 ))
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174 | {
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175 | tStart_3 = TCNT0;
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176 | }
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177 | if (!(PINB & ( 1 << PINB2 )) && (tStart_3!=0))
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178 | {
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179 | tWidth_3 = TCNT0 - tStart_3 - RC_OFFSET;
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180 | tStart_3 = 0;
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181 | }
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182 |
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183 | //Channel 4
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184 | if (PINB & ( 1 << PINB3 ))
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185 | {
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186 | tStart_4 = TCNT0;
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187 | }
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188 | if (!(PINB & ( 1 << PINB3 )) && (tStart_4!=0))
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189 | {
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190 | tWidth_4 = TCNT0 - tStart_4 - RC_OFFSET;
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191 | tStart_4 = 0;
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192 | }
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193 | }
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