1 | //******************************************************************************
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2 | // MSP-FET430P140 Demo - Basic Clock, Implement Auto RSEL SW FLL
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3 | //
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4 | // Description: Set DCO clock to (Delta)*(4096) using software FLL. DCO clock
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5 | // is output on P5.5 as SMCLK. DCO clock, which is the selected SMCLK source
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6 | // for timer_A is integrated over LFXT1/8 (4096) until SMCLK is is equal
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7 | // to Delta. CCR2 captures ACLK. To use Set_DCO Timer_A must be
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8 | // operating in continous mode. Watch crystal for ACLK is required for
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9 | // this example. Delta must be kept in a range that allows possible
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10 | // DCO speeds. Minimum Delta must ensure that Set_DCO loop
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11 | // can complete within capture interval. Maximum delta can be calculated be
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12 | // f(DCOx7) / 4096. f(DCOx7) can be found in device specific datasheet.
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13 | // ACLK = LFXT1/8 = 32768/8, MCLK = SMCLK = target DCO
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14 | // //* External watch crystal installed on XIN XOUT is required for ACLK *//
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15 | //
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16 | // MSP430F149
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17 | // ---------------
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18 | // /|\| XIN|-
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19 | // | | | 32kHz
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20 | // --|RST XOUT|-
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21 | // | |
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22 | // | P5.5|--> SMLCK = target DCO
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23 | // | P5.6|--> ALCK = 4096
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24 | //
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25 | //
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26 | // M. Buccini
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27 | // Texas Instruments Inc.
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28 | // Feb 2005
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29 | // Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
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30 | //******************************************************************************
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31 |
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32 | #include <msp430x14x.h>
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33 |
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34 | void Set_DCO (void);
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35 |
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36 | void main(void)
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37 | {
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38 | WDTCTL = WDTPW + WDTHOLD; // Stop WDT
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39 | P5DIR |= 0x60; // P5.5,6 output
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40 | P5SEL |= 0x60; // P5.5,6 SMCLK, ACLK output
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41 | Set_DCO(); // Set DCO
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42 |
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43 | while (1);
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44 | }
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45 |
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46 | //------------------------------------------------------------------------------
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47 | void Set_DCO (void) // Set DCO to selected frequency
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48 | //------------------------------------------------------------------------------
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49 | {
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50 | //#define DELTA 900 // target DCO = DELTA*(4096) = 3686400
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51 | #define DELTA 256 // target DCO = DELTA*(4096) = 1048576
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52 | //#define DELTA 70 // target DCO = DELTA*(4096) = 286720
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53 | unsigned int Compare, Oldcapture = 0;
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54 |
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55 | BCSCTL1 |= DIVA_3; // ACLK= LFXT1CLK/8
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56 | CCTL2 = CM_1 + CCIS_1 + CAP; // CAP, ACLK
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57 | TACTL = TASSEL_2 + MC_2 + TACLR; // SMCLK, cont-mode, clear
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58 |
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59 | while (1)
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60 | {
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61 | while (!(CCIFG & CCTL2)); // Wait until capture occured
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62 | CCTL2 &= ~CCIFG; // Capture occured, clear flag
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63 | Compare = CCR2; // Get current captured SMCLK
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64 | Compare = Compare - Oldcapture; // SMCLK difference
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65 | Oldcapture = CCR2; // Save current captured SMCLK
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66 |
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67 | if (DELTA == Compare) break; // If equal, leave "while(1)"
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68 | else if (DELTA < Compare) // DCO is too fast, slow it down
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69 | {
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70 | DCOCTL--;
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71 | if (DCOCTL == 0xFF)
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72 | {
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73 | if (!(BCSCTL1 == (XT2OFF + DIVA_3)))
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74 | BCSCTL1--; // Did DCO roll under?, Sel lower RSEL
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75 | }
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76 | }
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77 | else
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78 | {
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79 | DCOCTL++;
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80 | if (DCOCTL == 0x00)
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81 | {
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82 | if (!(BCSCTL1 == (XT2OFF + DIVA_3 + 0x07)))
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83 | BCSCTL1++; // Did DCO roll over? Sel higher RSEL
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84 | }
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85 | }
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86 | }
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87 | CCTL2 = 0; // Stop CCR2
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88 | TACTL = 0; // Stop Timer_A
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89 | }
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