endian.vhd

-- vlib work

-- vcom endian.vhd

-- vsim -gui endian_tb

-- add wave *

-- run -all

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity endian_tb is

end entity endian_tb;

architecture testbench of endian_tb is

    signal tb_data_i : std_logic_vector(0 to 7);

    signal tb_data_o : std_logic_vector(7 downto 0);

begin

    stimuli: process

    begin

        for index in 0 to 255 loop

            tb_data_i <= std_logic_vector( to_unsigned( index, tb_data_i'length));

            wait for 10 ns;

        end loop;

        wait; -- forever

    end process;

    dut: entity work.endian

    port map

    ( 

        data_i => tb_data_i,   -- : in  std_logic_vector(0 to 7);

        data_o => tb_data_o    -- : out std_logic_vector(7 downto 0)

    );

end architecture testbench;

library ieee;

use ieee.std_logic_1164.all;

entity endian is

    port

    ( 

        data_i : in  std_logic_vector(0 to 7);

        data_o : out std_logic_vector(7 downto 0)

    );

end entity endian;

architecture struct of endian is

begin

    data_o <= data_i;

end architecture struct;