interface.vhd


1
-- Zustände:  CONFIG_1, CONFIG_2, CONFIG_3, CH_SEL, GAIN_SWITCH, START, CONVERT, SAMPLE

2
--

3
--    CONFIG_1:    Konfiguration des 1 Slaves (nach Figure 46, Datenblatt zu ADS8332)

4
--    CONFIG_2:    Konfiguration aller anderen Slaves

5
--    CONFIG_3:    CFR (Konf.-Register) der Slaves auslesen

6
--    GAIN_SWITCH:  Gain-Umschaltung, serielle Uebertragung der Slave-Nr. (ADC-Board), des Kanals und der Verstärkung 

7
--    CH_SEL:      erster zu wandelnder Kanal wird eingestellt (i.d.R. Kanal 0), bevor die 1. Wandlung beginnt

8
--    START:      CONVST wird fuer mind. 20ns auf LOW gehalten; EOC-Pin des Wandler geht auf LOW

9
--    CONVERT:    Warten bis ADC fertig; wenn ADC fertig, EOC-Pin geht auf HIGH

10
--    SAMPLE:      Samplen der Eingangsspannung, Verzoegerung zum Einstellen der Abtastrate (siehe SAMPLE_DELAY)

11
--            Auslesen der Wandlungsergebnisse und gleichzeitig Wahl des naechsten Kanals per 4-Bit-Commando CMD

12
--

13
-- Senden der Ergebnisse einmal pro Wandlungszyklus an DSP-Board, ein Datenpaket pro Wandlung

14
-- Jeder Datenpaket an DSP erhaelt einen Timestamp aus 4 Byte Timestamp = aktueller Wert des Zaehlers stamp_cnt

15
--

16
--

17
18
library ieee;

19
use ieee.std_logic_1164.all;

20
use ieee.std_logic_arith.all;

21
use ieee.std_logic_unsigned.all;

22
use ieee.numeric_std.all;

23
use WORK.types.all;

24
25
entity interface is

26
  generic (CONFIG_par  : integer := 1;

27
       DATA_LENGTH : integer := DATA_LENGTH;

28
       SS_NUMBER   : integer := SS_NUMBER;

29
       SPI_NUMBER  : integer := SPI_NUMBER);

30
31
  port (

32
    CLK      : in std_logic; --CLK_PLL

33
    RST_I      : in std_logic;

34
35
    SS_MASTER_AR  : out SsVectorArray(0 to SPI_NUMBER-1);

36
    MOSI_MASTER_AR  : out std_logic_vector(0 to SPI_NUMBER-1);

37
    MISO_MASTER_AR  : in  std_logic_vector(0 to SPI_NUMBER-1);

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    SCLK_MASTER_AR  : out std_logic_vector(0 to SPI_NUMBER-1);

39
    RTS_MASTER_AR  : in  std_logic_vector(0 to SPI_NUMBER-1);

40
    SS_PR_MASTER  : out std_logic;

41
    MOSI_PR_MASTER  : out std_logic;

42
    MISO_PR_MASTER  : in std_logic;

43
    SCLK_PR_MASTER  : out std_logic;

44
    STATE_out    : out std_logic_vector(2 downto 0);    --EDIT: nur Testausgang !!!

45
    PACK_START    : out std_logic;              --EDIT: nur Testausgang !!!

46
    LED_1      : out std_logic;

47
    LED_2      : out std_logic

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    --RST_out      : out std_logic

49
    );

50
end;

51
52
architecture arch of interface is

53
  

54
  component spi_master

55
    generic (

56
        SHIFT_DIRECTION  : std_logic := '0';

57
        CLOCK_PHASE    : std_logic := '1';

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        CLOCK_POLARITY  : std_logic := '0';

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        CLOCK_SEL    : integer   := 8;    -- SCLK = CLK_I / (2*(CLOCK_SEL+1))

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        MASTER      : boolean   := True;

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        SS_NUMBER    : integer  := SS_NUMBER;

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        DATA_LENGTH    : integer   := 16;

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        DELAY_TIME    : integer   := 0;

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        DELAY_SS    : integer  := 0;

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        CLKCNT_WIDTH  : integer   := 5;

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        INTERVAL_LENGTH  : integer   := 2);

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    port (

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      DATA_IN    : in  std_logic_vector(DATA_LENGTH-1 downto 0);

69
      DATA_OUT  : out std_logic_vector(DATA_LENGTH-1 downto 0);

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      SS_IN    : in  std_logic_vector(SS_NUMBER-1 downto 0);

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      MISO_MASTER  : in  std_logic;

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      MOSI_MASTER  : out std_logic;

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      --SS_N_MASTER  : out std_logic;

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      SS_N_MASTER  : out std_logic_vector(SS_NUMBER-1 downto 0);

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      SCLK_MASTER  : out std_logic;

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      CLK_I    : in  std_logic;

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      RST_I    : in  std_logic;

78
      TX_RDY    : out std_logic;

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      RX_RDY    : out std_logic;

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      TX_OER    : out std_logic;

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      RX_OER    : out std_logic;

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      TRIG_WR_RD  : in  std_logic;

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      READ_DATA  : in std_logic

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      );

85
  end component;

86
  

87
  component debounce

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    Port ( CLK    : in  std_logic;

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         keyin  : in  std_logic;

90
         keyout : out  std_logic);

91
  end component;

92
  

93
  component pll

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    port (CLK: in std_logic; CLKOP: out std_logic; LOCK: out std_logic);

95
  end component;

96
97
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  signal CLK_PLL        : std_logic;

99
  signal pll_lock        : std_logic;

100
  

101
  signal spi_paket_s      : SPIDATNEU;-- := (x"00", x"00", x"00", x"00", x"0000", (others => x"00"), x"0000");

102
  

103
  

104
  signal spi_trm_buff_s    : SPI_BUFF;

105
  

106
  signal stamp_cnt      : std_logic_vector(31 downto 0);

107
  

108
  signal RST          : std_logic;-- := '0';

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  signal rst_cnt        : integer range 0 to 5000000 := 0;

110
111
  signal ss_in_pr_master    : std_logic_vector(SS_NUMBER-1 downto 0); -- := "111";

112
  signal ss_pr_master_s    : std_logic_vector(SS_NUMBER-1 downto 0);

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  signal d_in_pr_master    : std_logic_vector(7 downto 0); --(DATA_LENGTH-1 downto 0);

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  signal d_out_pr_master    : std_logic_vector(7 downto 0); --(DATA_LENGTH-1 downto 0);

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  signal tx_rdy_pr_master    : std_logic;

116
  signal tx_rdy_pr_last    : std_logic;

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  signal tx_rdy_pr_rising    : std_logic;

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  signal rx_rdy_pr_master    : std_logic;

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  signal tx_oer_pr_master    : std_logic;

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  signal rx_oer_pr_master    : std_logic;

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  signal wr_rd_pr_master    : std_logic;

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  signal rd_data_pr_master  : std_logic;

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  signal pr_master_wr_flag  : std_logic; -- := '0';

124
  

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  signal ss_master_ar_s    : SsVectorArray(0 to SPI_NUMBER-1);

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  signal ss_in_master_ar_s  : SsVectorArray(0 to SPI_NUMBER-1);

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  signal rts_master_ar_s    : std_logic_vector(0 to SPI_NUMBER-1);

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  signal d_in_master_ar_s    : DataVectorArray(0 to SPI_NUMBER-1);

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  signal d_out_master_ar_s  : DataVectorArray(0 to SPI_NUMBER-1);

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  signal tx_rdy_master_ar_s  : std_logic_vector(0 to SPI_NUMBER-1);

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  signal tx_rdy_last_ar_s    : std_logic_vector(0 to SPI_NUMBER-1);

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  signal tx_rdy_rising_ar_s  : std_logic_vector(0 to SPI_NUMBER-1);

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  signal rx_rdy_master_ar_s  : std_logic_vector(0 to SPI_NUMBER-1);

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  signal rx_rdy_last_ar_s    : std_logic_vector(0 to SPI_NUMBER-1);

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  signal rx_rdy_rising_ar_s  : std_logic_vector(0 to SPI_NUMBER-1);

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  signal tx_oer_master_ar_s  : std_logic_vector(0 to SPI_NUMBER-1);

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  signal rx_oer_master_ar_s  : std_logic_vector(0 to SPI_NUMBER-1);

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  signal wr_rd_master_ar_s  : std_logic_vector(0 to SPI_NUMBER-1);

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  signal rd_data_master_ar_s  : std_logic_vector(0 to SPI_NUMBER-1);

140
  signal master_wr_flag_ar_s  : std_logic_vector(0 to SPI_NUMBER-1);

141
  signal rx_packet_rdy_s    : std_logic_vector(0 to SPI_NUMBER-1);

142
    

143
  signal convst_s      : std_logic; -- := '1';

144
  signal rd_byte_cnt    : integer range 0 to 7;

145
  signal ss_trans_ar_s  : SsVectorArray(0 to SPI_NUMBER-1);

146
  

147
  signal test        : std_logic;

148
  signal send_flag    : std_logic;

149
  signal send_ready_flag  : std_logic;

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  signal transm_flag    : std_logic;

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  signal cnt        : integer range 0 to 3328;

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  signal transm_cnt    : integer range 0 to SPI_DATA_LENGTH-1+8; --SPI_NUMBER-1;

153
  type slave_cnt_array is array (0 to SPI_NUMBER) of integer range 0 to SLAVE_NUMBER-1;

154
  signal slave_cnt_ar_s  : slave_cnt_array;

155
  signal cfg_start    : std_logic;

156
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  signal sSpiWait    : std_logic;  -- high, when state = CONFIG_1 till CONFIG_3 and spi-modules are active (sending data)

158
159
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  type states  is (CONFIG_1, CONFIG_2, CONFIG_3, CH_SEL, START, CONVERT, SAMPLE); --GAIN_SWITCH);

161
  signal state, next_state : states;

162
    

163
  signal RST_deb    : std_logic;

164
  

165
  signal master_no    : std_logic_vector(2 downto 0);

166
  signal sChanNum      : std_logic_vector(15 downto 0);

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  signal sChanNum2    : integer range  0 to 7;--std_logic_vector(3 downto 0);

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  signal sChanSelFlag    : std_logic;

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  signal sPackStart    : std_logic;

170
  

171
  

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  signal led_cnt      : integer range 0 to 67100000; -- std_logic_vector(25 downto 0);

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  signal gain_cnt      : integer range 0 to 67100000;

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  signal led_1_s      : std_logic;-- := '1';

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  signal led_2_s      : std_logic;-- := '0';

176
  

177
  signal state_out_s    : std_logic_vector(2 downto 0);-- := "000";

178
  

179
  signal gain_sel_flag      : std_logic;-- := '0';

180
  signal gain        : std_logic_vector(2 downto 0);-- := "000";

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  signal chan        : std_logic_vector(2 downto 0);-- := "000";

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  signal gain_switch_flag  : std_logic;--             := '1';

183
  

184
  

185
186
begin

187
  

188
  rts : for m in 0 to SPI_NUMBER-1 generate

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    rts_master_ar_s(m) <= RTS_MASTER_AR(m);

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    -- SS_MASTER_AR(m) <= convst_s & ss_master_ar_s(m)(1) & ss_master_ar_s(m)(0);

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    SS_MASTER_AR(m) <= ss_master_ar_s(m) when state /= START else "011";

192
    -------------------------------------------------------------------------------------------------------------

193
    --  Notice: information on assignement of vector array bits to FPGA ports in C:\Daten\SIB\Vectror_array_assignment.xls !!!!

194
    end generate;

195
    

196
  --RST_out <= RST;

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  PACK_START <= sPackStart;

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  SS_PR_MASTER <= ss_pr_master_s(0);

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  send_flag <= '1' when (rx_packet_rdy_s = (rx_packet_rdy_s'range => '1')) else '0';

200
  

201
  LED_1 <= led_1_s;

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  LED_2 <= led_2_s;

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  STATE_out <= state_out_s;

204
  

205
  pll_c : pll

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    port map (CLK => CLK, CLKOP=> CLK_PLL, LOCK=> pll_lock);

207
    

208
  spi_pr_master_c : spi_master

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    generic map( CLOCK_SEL => 0, DATA_LENGTH => 8, DELAY_TIME => 0, INTERVAL_LENGTH => 0)

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    port map( d_in_pr_master, d_out_pr_master, ss_in_pr_master, MISO_PR_MASTER, MOSI_PR_MASTER, ss_pr_master_s, SCLK_PR_MASTER,

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        CLK_PLL, RST, tx_rdy_pr_master, rx_rdy_pr_master, tx_oer_pr_master, rx_oer_pr_master, wr_rd_pr_master, rd_data_pr_master );

212
213
214
  GEN_MASTER : for I in 0 to SPI_NUMBER-1 generate

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    spi_master_i : spi_master

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      port map(  DATA_IN     => d_in_master_ar_s(I),

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          DATA_OUT     => d_out_master_ar_s(I),

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           SS_IN       => ss_in_master_ar_s(I),

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           MISO_MASTER   => MISO_MASTER_AR(I),

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           MOSI_MASTER   => MOSI_MASTER_AR(I),

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           SS_N_MASTER   => ss_master_ar_s(I),

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           SCLK_MASTER   => SCLK_MASTER_AR(I),

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           CLK_I       => CLK_PLL,

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           RST_I       => RST,

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           TX_RDY     => tx_rdy_master_ar_s(I),

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           RX_RDY     => rx_rdy_master_ar_s(I),

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           TX_OER     => tx_oer_master_ar_s(I),

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           RX_OER     => rx_oer_master_ar_s(I),

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           TRIG_WR_RD   => wr_rd_master_ar_s(I),

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           READ_DATA     => rd_data_master_ar_s(I));

231
  end generate;

232
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  process (RST, CLK_PLL, state) begin

235
    if RST = '0' then

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      led_cnt <= 0;

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      led_1_s <= '1';

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      led_2_s <= '0';

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    elsif CLK_PLL = '1' and CLK_PLL'event and state = SAMPLE then

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      if led_cnt /= 67100000 then

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        led_cnt <= led_cnt + 1;

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      else

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        led_cnt <= 0;

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        led_1_s <= not led_1_s;

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        led_2_s <= not led_2_s;

246
      end if;

247
    end if;

248
  end process;

249
250
  

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252
253
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  process (CLK_PLL, RST) begin

255
    if RST = '0' then

256
      spi_trm_buff_s <= (others=> X"00");

257
    elsif CLK_PLL = '1' and CLK_PLL'event then

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      if send_flag = '1' then

259
        for k in 0 to SPI_DATA_LENGTH-1 loop

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          spi_trm_buff_s(0)    <= spi_paket_s.CMD;-- & spi_paket_s.ID;

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          spi_trm_buff_s(1)    <= spi_paket_s.ID;

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          spi_trm_buff_s(2)    <= spi_paket_s.TYPE_h;-- & spi_paket_s.SUB_CMD;

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          spi_trm_buff_s(3)    <= spi_paket_s.SUB_CMD;

264
          spi_trm_buff_s(4)    <= spi_paket_s.LEN(15 downto 8);

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          spi_trm_buff_s(5)    <= spi_paket_s.LEN(7 downto 0);

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          spi_trm_buff_s(6+k)   <= spi_paket_s.Daten(k);

267
          spi_trm_buff_s(SPI_DATA_LENGTH+6)    <= spi_paket_s.EDC(15 downto 8);

268
          spi_trm_buff_s(SPI_DATA_LENGTH+7)    <= spi_paket_s.EDC(7 downto 0);

269
        end loop;

270
      end if;

271
    --elsif rcv_rdy = '1' and spi_rcv_buff_s(0) = X"44" then

272
      --empfangen Daten zurücksenden

273
      --spi_trm_buff_s <= spi_rcv_buff_s;

274
    --end if;

275
    end if;

276
  end process;

277
  

278
  --***************************** RESET ***********************************************************************

279
  

280
  --RESET : process (RST_deb, pll_lock) begin

281
  --  if RST_deb = '1' and pll_lock = '1' then

282
  --    RST <= '1';

283
  --  else

284
  --    RST <= '0';

285
  --  end if;

286
  --end process RESET;

287
288
  process (CLK_PLL)

289
  --variable rst_cnt : integer range 0 to 5000000 := 0;

290
  begin

291
    if (CLK_PLL'event and CLK_PLL = '1') then

292
      RST <= '0';

293
      if pll_lock = '1' then

294
        if rst_cnt /= 5000000 then

295
          --rst_cnt := rst_cnt + 1;

296
          rst_cnt <= rst_cnt + 1;

297
          RST <= '0';

298
        --elsif RST_deb = '1' and rst_cnt = 5000000 then

299
        --  --rst_cnt <= 0;

300
        --  RST <= '1';

301
        else RST <= '1';

302
        end if;

303
      end if;

304
    end if;

305
  end process;

306
307
  --****************************************************************************************************************

308
  

309
  stamp : process (CLK_PLL, RST) begin

310
    if RST = '0' then

311
      stamp_cnt <= X"00000000";

312
      --stamp_cnt <= X"00";

313
    elsif CLK_PLL = '1' and CLK_PLL'event then

314
      stamp_cnt <= stamp_cnt + 1;

315
    end if;

316
  end process stamp;

317
  

318
  

319
  state_reg : process (CLK_PLL, RST) begin

320
    if RST = '0' then

321
      if CONFIG_par = 1 then

322
        state <=  CONFIG_1; --GAIN_TEST;

323
      else

324
        state <= START;

325
      end if;

326
    elsif CLK_PLL = '1' and CLK_PLL'event then

327
      state <= next_state;-- after 5 ns;

328
    end if;

329
  end process state_reg;

330
  

331
  -- cnt handling

332
  cntr : process (CLK_PLL, RST) begin

333
      if RST = '0' then

334
        cnt <= 0;

335
      elsif CLK_PLL = '1' and CLK_PLL'event then

336
        case state is

337
          --when GAIN_SWITCH  =>  cnt <= 0;

338
          when CONFIG_1    =>  cnt <= 0;

339
          when CONFIG_2    =>  cnt <= 0;

340
          when CONFIG_3    =>  cnt <= 0;

341
          when CH_SEL      =>  cnt <= 0;

342
          when START    =>  if cnt < 4 then

343
                      cnt <= cnt + 1;

344
                    elsif cnt >= 4 and rts_master_ar_s(0) = '0' then

345
                      cnt <= 0;

346
                    end if;

347
          when CONVERT  =>  cnt <= 0;

348
          when SAMPLE    =>  if cnt < SAMPLE_DELAY then --940s

349
                      cnt <= cnt + 1;

350
                    else cnt <= 0; 

351
                    end if;

352
        end case;

353
      end if;

354
  end process cntr;

355
356
  

357
  ns_decoder : process (RST, rts_master_ar_s, cnt, rx_rdy_rising_ar_s, state, sSpiWait) begin      --EDIT: sensitivity list OK??

358
    if RST = '0' then

359
      gain_switch_flag <= '1';

360
      next_state <= CONFIG_1;

361
    else

362
      case state is

363
        -- when GAIN_TEST =>  if state = GAIN_TEST and sSpiWait = '1' and rx_rdy_rising_ar_s(0) = '1' and chan = "111" then next_state <= CONFIG_1;

364
                  -- else next_state <= GAIN_TEST;

365
                  -- end if;

366
        -- when CONFIG_1 =>  if state = CONFIG_1 and sSpiWait = '1' and gain_sel_flag = '0' and rx_rdy_rising_ar_s(0) = '1' then next_state <= CONFIG_2;

367
        when CONFIG_1 =>  if state = CONFIG_1 and sSpiWait = '1' and rx_rdy_rising_ar_s(0) = '1' then next_state <= CONFIG_2;

368
                  else next_state <= CONFIG_1;

369
                  end if;

370
        -- when CONFIG_2 =>  if state = CONFIG_2 and sSpiWait = '1' and gain_sel_flag = '0' and rx_rdy_rising_ar_s(0) = '1' then next_state <= CONFIG_3;

371
        when CONFIG_2 =>  if state = CONFIG_2 and sSpiWait = '1' and rx_rdy_rising_ar_s(0) = '1' then next_state <= CONFIG_3;

372
                  else next_state <= CONFIG_2;

373
                  end if;

374
        -- when CONFIG_3 =>  if state = CONFIG_3 and sSpiWait = '1' and gain_sel_flag = '0' and rx_rdy_rising_ar_s(0) = '1' then next_state <= CH_SEL;      -- EDIT hier state CONFIG_3 erweitern, abfrage und pruefung der konfiguration

375
        when CONFIG_3 =>  next_state <= CH_SEL;

376
                  --if state = CONFIG_3 and sSpiWait = '1' and rx_rdy_rising_ar_s(0) = '1' then next_state <= CH_SEL;

377
                  --else next_state <= CONFIG_3;

378
                  --end if;

379
        when CH_SEL =>    if state = CH_SEL and sSpiWait = '1' and rx_rdy_rising_ar_s(0) = '1' then next_state <= START;

380
                  else next_state <= CH_SEL;

381
                  end if;

382
        when START  =>    --if gain_switch_flag = '1' and rts_master_ar_s(0) = '1' then next_state <= GAIN_SWITCH;

383
                  if cnt >= 2 and rts_master_ar_s(0) = '0' then next_state <= CONVERT;

384
                  else next_state <= START;

385
                  end if;

386
        when CONVERT =>    if rts_master_ar_s(0) = '1' then next_state <= SAMPLE; --and rts_master_ar_s(1) = '1' then next_state <= SAMPLE;

387
                  else next_state <= CONVERT;

388
                  end if;

389
        when SAMPLE =>    if cnt = SAMPLE_DELAY and rts_master_ar_s(0) = '1' then next_state <= START;  --3400

390
                  else next_state <= SAMPLE;

391
                  end if;

392
        -- when GAIN_SWITCH => if state = GAIN_SWITCH and sSpiWait = '1' and gain_sel_flag = '0' and rx_rdy_rising_ar_s(0) = '1' then next_state <= START;           gain_switch_flag <= '0';--if

393
                  -- else next_state <= GAIN_SWITCH;

394
                  -- end if;

395
        --when others =>    null;

396
      end case;

397
    end if;

398
    --end loop;

399
  end process ns_decoder;

400
  

401
  out_decoder : process (state, RST) begin

402
    if RST = '0' then

403
      state_out_s <= "000";

404
    else

405
    case state is

406
      -- when GAIN_SWITCH =>  convst_s <= '1';

407
                -- state_out_s <= "001";

408
      when CONFIG_1 =>  convst_s <= '1';

409
                state_out_s <= "001";

410
      when CONFIG_2 =>  convst_s <= '1';

411
                state_out_s <= "010";

412
      when CONFIG_3 =>  convst_s <= '1';

413
                state_out_s <= "011";

414
      when CH_SEL =>    convst_s <= '1';

415
                state_out_s <= "100";

416
      when START =>    convst_s <= '0';

417
                state_out_s <= "101";

418
      when CONVERT =>    convst_s <= '1';

419
                state_out_s <= "110";

420
      when SAMPLE =>    convst_s <= '1';

421
                state_out_s <= "111";

422
    end case;

423
    end if;

424
  end process out_decoder;

425
  

426
  spi : process (CLK_PLL, RST) begin

427
    if (RST = '0') then

428
      rd_byte_cnt <= 0;

429
      for m in 0 to SPI_NUMBER-1 loop

430
        ss_in_master_ar_s(m) <= "111";

431
        ss_trans_ar_s(m) <= "100"; --"010";    --EDIT: ss_trans_ar_s -> Signal nicht mehr noetig !!!!!

432
        d_in_master_ar_s(m) <= (OTHERS => '1');

433
        tx_rdy_rising_ar_s(m) <= '1';

434
        tx_rdy_last_ar_s(m) <= '1';

435
        wr_rd_master_ar_s(m) <= '0';

436
      end loop;

437
      sSpiWait <= '0';

438
      gain_sel_flag <= '0';

439
      --sChanNum <= X"0000"; -- X"1000";

440
      sChanNum2 <= 0;--"0000";

441
      sPackStart <= '0';

442
      sChanSelFlag <= '1';

443
      

444
    elsif (CLK_PLL'event and CLK_PLL = '1') then

445
    

446
      for m in 0 to SPI_NUMBER-1 loop

447
      tx_rdy_last_ar_s(m) <= tx_rdy_master_ar_s(m);

448
      tx_rdy_rising_ar_s(m) <= tx_rdy_master_ar_s(m) and not tx_rdy_last_ar_s(m);

449
      end loop;

450
451
452
      --***************************** CONFIG 1 ************************************************************************

453
454
455
456
      if state = CONFIG_1 and sSpiWait = '0' and tx_rdy_master_ar_s(0) = '1' then

457
        sSpiWait <= '1';

458
        for m in 0 to SPI_NUMBER-1 loop

459
        ss_in_master_ar_s(m) <= "110"; -- configure slave 1

460
        --d_in_master_ar_s(m) <= "1100000000000000";

461
        d_in_master_ar_s(m) <= "1110011111111101";  -- write CFR '1110', man chan sel, int clk, man trig, eoc activ low, all pow-dwn dis,

462
                                                    -- no tag-bits

463
        wr_rd_master_ar_s(m) <= '1';

464
        end loop;

465
      elsif state = CONFIG_1 and wr_rd_master_ar_s(0) = '1' then

466
        for m in 0 to SPI_NUMBER-1 loop

467
        wr_rd_master_ar_s(m) <= '0';

468
        end loop;

469
      elsif state = CONFIG_1 and sSpiWait = '1' and rx_rdy_rising_ar_s(0) = '1' then

470
        sSpiWait <= '0';

471
472
473
      --***************************** CONFIG 2 ************************************************************************

474
475
      elsif state = CONFIG_2 and sSpiWait = '0' and tx_rdy_master_ar_s(0) = '1' then

476
        sSpiWait <= '1';

477
        for m in 0 to SPI_NUMBER-1 loop

478
        ss_in_master_ar_s(m) <= "101";  -- configure slave 2

479
        d_in_master_ar_s(m) <= "1110011111111101";  -- write CFR '1110', man chan sel, int clk, man trig, eoc activ low, all pow-dwn dis,

480
                                                    -- no tag-bits

481
        wr_rd_master_ar_s(m) <= '1';

482
        end loop;

483
      elsif state = CONFIG_2 and wr_rd_master_ar_s(0) = '1' then

484
        for m in 0 to SPI_NUMBER-1 loop

485
        wr_rd_master_ar_s(m) <= '0';

486
        end loop;

487
      elsif state = CONFIG_2 and sSpiWait = '1' and rx_rdy_rising_ar_s(0) = '1' then

488
        sSpiWait <= '0';

489
490
491
492
      --***************************** CONFIG 3 ************************************************************************

493
494
495
496
      --***************************** CH SEL ****************************************************************************

497
      

498
      elsif state = CH_SEL and sSpiWait = '0' and tx_rdy_master_ar_s(0) = '1' then

499
        sSpiWait <= '1';

500
        for m in 0 to SPI_NUMBER-1 loop

501
        ss_in_master_ar_s(m) <= "100";  -- channel select on all slaves (ADCs)

502
        d_in_master_ar_s(m) <= std_logic_vector(to_unsigned(sChanNum2,4))&X"000";--sChanNum; -- X"0000";

503
        -- sChanNum <= sChanNum + X"1000";

504
        wr_rd_master_ar_s(m) <= '1';

505
        end loop;

506
      elsif state = CH_SEL and wr_rd_master_ar_s(0) = '1' then

507
        for m in 0 to SPI_NUMBER-1 loop 

508
        wr_rd_master_ar_s(m) <= '0';

509
        end loop;

510
      elsif state = CH_SEL and sSpiWait = '1' and rx_rdy_rising_ar_s(0) = '1' then

511
        sSpiWait <= '0';

512
      end if;

513
      

514
  -- *****************************  ERGEBNISSE DER WANDLUNG AUSLESEN ********************************************************

515
    

516
      if state = CONVERT and next_state = SAMPLE then

517
        rd_byte_cnt <= SLAVE_NUMBER;

518
      end if;

519
      for m in 0 to SPI_NUMBER-1 loop

520
      if rd_byte_cnt > 0 and tx_rdy_master_ar_s(m) = '1' and wr_rd_master_ar_s(m) = '0' then

521
        d_in_master_ar_s(m) <= std_logic_vector(to_unsigned(sChanNum2,4))&X"000";--sChanNum;

522
        ss_in_master_ar_s(m) <= "100";

523
        ss_trans_ar_s(m) <= "100"; --"010";

524
        wr_rd_master_ar_s(m) <= '1';

525
      elsif rd_byte_cnt > 0 and wr_rd_master_ar_s(m) = '1' then

526
        wr_rd_master_ar_s(m) <= '0';

527
        rd_byte_cnt <= rd_byte_cnt - 1;

528
      end if;

529
      end loop;

530
      

531
      if state = START and next_state = CONVERT then --and sChanSelFlag = '1' then

532
        

533
        --if sChanNum2 < 7 then

534
        --  sChanNum2 <= sChanNum2 + 1;

535
        --  sPackStart <= '1';

536
        --else

537
        --  sChanNum2 <= 0;

538
        --  sPackStart <= '0';

539
        --end if;

540
        if sChanNum2 = 7 then--"0111" then

541
          sChanNum2 <= 0;--"0000";

542
          sPackStart <= '0';

543
        else

544
          sChanNum2 <= sChanNum2 + 1;

545
          --if sPackStart = '0' then sPackStart <= '1'; end if;  -- EDIT: for debugging, delete later

546
          sPackStart <= '1';

547
        end if;

548
                

549
        --sChanSelFlag <= '0';

550
      end if;

551
    end if;

552
  end process spi;

553
  

554
555
  receive : process (CLK_PLL, RST) begin

556
    --for m in 0 to SPI_NUMBER-1 loop

557
    if(RST = '0') then

558
      spi_paket_s.CMD    <= x"81";

559
      spi_paket_s.ID    <= x"00";

560
      spi_paket_s.TYPE_h  <= x"00";

561
      spi_paket_s.SUB_CMD  <= x"00";

562
      spi_paket_s.LEN    <= x"0000";

563
      spi_paket_s.EDC    <= x"0000";

564
      spi_paket_s.Daten  <= (others => x"00");

565
      for m in 0 to SPI_NUMBER-1 loop

566
      --for n in 0 to SLAVE_NUMBER-1 loop

567
      --end loop;  

568
      rd_data_master_ar_s(m) <= '0';

569
      rx_rdy_rising_ar_s(m) <= '0';

570
      rx_rdy_last_ar_s(m) <= '0';

571
      rx_packet_rdy_s(m) <= '0';

572
      slave_cnt_ar_s(m) <= 0;

573
      end loop;

574
      ----spi_paket_s.Daten  <= (others => x"00");

575
      ----spi_paket_s.ID    <= x"00";

576
577
    elsif (CLK_PLL'event and CLK_PLL = '1') then

578
      if state = START and next_state = CONVERT then

579
        spi_paket_s.Daten(2) <= stamp_cnt(7 downto 0);

580
        spi_paket_s.Daten(3) <= stamp_cnt(15 downto 8);

581
        spi_paket_s.Daten(4) <= stamp_cnt(23 downto 16);

582
        spi_paket_s.Daten(5) <= stamp_cnt(31 downto 24);

583
        --spi_paket_s.ID     <= ("0000"&sChanNum(15 downto 12));

584
        spi_paket_s.ID <= ("0000"&std_logic_vector(to_unsigned(sChanNum2,4)));

585
      end if;      

586
      for m in 0 to SPI_NUMBER-1 loop

587
      rx_rdy_last_ar_s(m) <= rx_rdy_master_ar_s(m);

588
      rx_rdy_rising_ar_s(m) <= rx_rdy_master_ar_s(m) and not rx_rdy_last_ar_s(m);

589
      if rx_rdy_rising_ar_s(m) = '1' then

590
        if state = SAMPLE then

591
          if slave_cnt_ar_s(m) = SLAVE_NUMBER-1 then

592
            spi_paket_s.Daten(6+2*m*SLAVE_NUMBER+2*slave_cnt_ar_s(m)) <= d_out_master_ar_s(m)(7 downto 0);

593
            spi_paket_s.Daten(6+2*m*SLAVE_NUMBER+2*slave_cnt_ar_s(m)+1) <= d_out_master_ar_s(m)(15 downto 8);

594
            slave_cnt_ar_s(m) <= 0;

595
            rx_packet_rdy_s(m) <= '1';

596
          else

597
            spi_paket_s.Daten(6+2*m*SLAVE_NUMBER+2*slave_cnt_ar_s(m)) <= d_out_master_ar_s(m)(7 downto 0);

598
            spi_paket_s.Daten(6+2*m*SLAVE_NUMBER+2*slave_cnt_ar_s(m)+1) <= d_out_master_ar_s(m)(15 downto 8);

599
            slave_cnt_ar_s(m) <= slave_cnt_ar_s(m) + 1;

600
          end if;

601
          rd_data_master_ar_s(m) <= '1';        -- EDIT: check effect of rd_data_master_ar_s !!!!!!!!

602
        else

603
          rd_data_master_ar_s(m) <= '1';

604
        end if;

605
      else

606
        rd_data_master_ar_s(m) <= '0';

607
        rx_packet_rdy_s(m) <= '0';

608
      end if;

609
      end loop;

610
    end if;

611
    --end loop;

612
  end process receive;

613
614
615
  send : process (CLK_PLL, RST) begin

616
    if (RST = '0') then

617
    send_ready_flag <= '0';

618
    wr_rd_pr_master <= '0';

619
    transm_cnt <= 0;

620
    transm_flag <= '0';

621
    d_in_pr_master <= (OTHERS => '0');

622
    ss_in_pr_master <= (OTHERS => '1');

623
    elsif (CLK_PLL'event and CLK_PLL = '1') then

624
      test <= '0';

625
      tx_rdy_pr_last <= tx_rdy_pr_master;

626
      tx_rdy_pr_rising <= tx_rdy_pr_master and not tx_rdy_pr_last;

627
      if send_flag = '1' then

628
        transm_flag <= '1';

629
        if tx_rdy_pr_master = '1' then

630
          test <= '1';

631
        end if;

632
      elsif transm_flag = '1' and (tx_rdy_pr_rising = '1' or test = '1') then

633
        d_in_pr_master <= spi_trm_buff_s(transm_cnt);

634
        ss_in_pr_master <= "110";

635
        wr_rd_pr_master <= '1';

636
        if transm_cnt /= SPI_DATA_LENGTH-1+8 then

637
          transm_cnt <= transm_cnt + 1;

638
        elsif transm_cnt = SPI_DATA_LENGTH-1+8 then

639
          transm_cnt <= 0;

640
          transm_flag <= '0';

641
        end if;

642
      else

643
        wr_rd_pr_master <= '0';

644
      end if;

645
    end if;

646
  end process send;

647
  

648
end arch;