uart.vhd

--------------------------------------------------------------------------------

-- Company: 

-- Engineer:

--

-- Create Date:    13:23:22 12/28/05

-- Design Name:    

-- Module Name:    sersenden - Behavioral

-- Project Name:   

-- Target Device:  

-- Tool versions:  

-- Description:

--

-- Dependencies:

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

-- 

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity uart is

generic(bitleng: integer:=(868-1));

port(serout: out std_logic:='1';

     clk: in std_logic;

    txenable: in std_logic;

    reset: in std_logic;

    serin: in std_logic;

    txbuffer: in std_logic_vector(7 downto 0);

     txerror: out std_logic:='0';

     rxready: out std_logic:='0';

     rxbuffer: out std_logic_vector(7 downto 0);

     txbusy: out std_logic:='0';

     rxerror: out std_logic:='0'

);

end uart;

architecture uneu of uart is

signal statussenden: integer range 0 to 4:=0;

signal counterout: integer range 0 to 1023:=0;

signal statusempfang: integer range 0 to 4:=0;

signal counterin: integer range 0 to 1023:=0;

signal txstartbuffer: std_logic_vector(7 downto 0):=x"00";

signal rxempfangen:std_logic_vector(7 downto 0):=x"FF";

signal txstart:std_logic:='0';

signal txbusyser: std_logic:='0';

signal sperren: std_logic:='0';

begin

seroutx: process(clk,reset,statussenden)

variable counter2: integer range 0 to 7:=0;

variable txsenden:std_logic_vector(7 downto 0):=x"00";

begin

if reset='1' then

if clk'event and clk='1'then

case statussenden is

 when 0 => if txstart='1' then    -- Warten auf Start und starten.

           serout<='0';

           statussenden<=1;

        counter2:=0;

        counterout<=0;

        txbusyser<='1';

        txsenden:=txstartbuffer;

        end if;

 when 1 => counterout<=counterout+1;   -- Byte rausschieben

           if counterout>=bitleng then

          counterout<=0;

             serout<=txsenden(counter2);

             if counter2>=7 then

          statussenden<=2;

          else

          counter2:=counter2+1;

          end if;

           end if;

 when 2 => counterout<=counterout+1;   -- Beginn des Stoppbits

           txbusyser<='0';

           if counterout>=bitleng then

           counterout<=0;

              serout<='1';

           statussenden<=3;        

        end if;

 when 3 => counterout<=counterout+1;   -- Ende des Stoppbits und wenn nötig einleiten des nächsten Starts.

           if counterout>=bitleng then

          counterout<=0;

          if txstart='1' then

                 serout<='0';

                 statussenden<=1;

              counter2:=0;

              txsenden:=txstartbuffer;

              txbusyser<='1';

          else

             statussenden<=0;

          end if;

        end if;

 when others => null;

end case;

end if;

--end if;

else

serout<='1';

counterout<=0;

statussenden<=0;

end if;

end process seroutx;

serstarten: process(txenable,txbusyser,reset)

begin

if reset='1' then

  if txbusyser = '1' then

    txstart<='0';

    --start<='0';

    else

      if txenable'event and txenable='1' then

        txstart<='1';

           txstartbuffer<=txbuffer;

         end if;

   end if;

else

  --sperren:=0;

  txstart<='0';

end if;

end process serstarten;

serinx: process(clk,serin,reset)

variable counter2x: integer range 0 to 7:=0;

variable errorstart: std_logic:='0';

begin

if reset='1' then

if clk='1' and clk'event then

case statusempfang is

when 0 => if (serin='0' and errorstart='0') then

             statusempfang<=1;

         counterin<=bitleng/2;

         counter2x:=0;

       end if;

          if (serin='1' and errorstart='1') then

          errorstart:='0';

          end if;

when 1 => counterin<=counterin+1;

          if counterin>=bitleng then

          statusempfang<=2;

         counterin<=0;

         rxready<='0';

          end if;

when 2 => counterin<=counterin+1;

          if counterin>=bitleng then

          rxempfangen(counter2x)<=serin;

         counterin<=0;

         --counter2<=counter2+1;

         if counter2x >= 7 then

          statusempfang<=3;

         counterin<=0;

         else

         counter2x:=counter2x+1;

          end if;

          end if;

when 3 => counterin<=counterin+1;

          if counterin>=bitleng then

          if serin='1' then

             statusempfang<=0;

         rxbuffer<=rxempfangen;

         rxerror<='0';

         rxready<='1';

         --outx4<='1';

          else

          statusempfang<=0;

          rxerror<='1';

         errorstart:='1';

         rxready<='1';

          end if;

       end if;

when others => null;

end case;

end if;

else

-- Reset

rxerror<='0';

errorstart:='0';

rxready<='0';

rxbuffer <=(others=>'0');

end if;

end process serinx;

txbusy<=txbusyser or txstart;

end uneu;