Digitaluhr.vhd


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----------------------------------------------------------------------------------

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-- Company: 

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-- Engineer: 

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-- 

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-- Create Date:    18:05:30 12/12/2014 

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-- Design Name: 

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-- Module Name:    Digitaluhr - Behavioral 

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-- Project Name: 

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-- Target Devices: 

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-- Tool versions: 

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-- Description: 

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--

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-- Dependencies: 

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--

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-- Revision: 

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-- Revision 0.01 - File Created

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-- Additional Comments: 

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--

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----------------------------------------------------------------------------------

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_unsigned.ALL;

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-- Uncomment the following library declaration if using

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-- arithmetic functions with Signed or Unsigned values

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use IEEE.NUMERIC_STD.ALL;

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-- Uncomment the following library declaration if instantiating

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-- any Xilinx primitives in this code.

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--library UNISIM;

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--use UNISIM.VComponents.all;

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entity Digitaluhr is

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    Port ( clk : in  STD_LOGIC;

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           reset : in  STD_LOGIC;

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        stunde : in STD_LOGIC;

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        mode : in STD_LOGIC_VECTOR (1 downto 0);

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           o_std_z : out  STD_LOGIC_VECTOR (3 downto 0);

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           o_std_e : out  STD_LOGIC_VECTOR (3 downto 0);

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           o_min_z : out  STD_LOGIC_VECTOR (3 downto 0);

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           o_min_e : out  STD_LOGIC_VECTOR (3 downto 0);

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           o_sec_z : out  STD_LOGIC_VECTOR (3 downto 0);

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           o_sec_e : out  STD_LOGIC_VECTOR (3 downto 0);

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       i_std_z : in  STD_LOGIC_VECTOR (3 downto 0);

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           i_std_e : in  STD_LOGIC_VECTOR (3 downto 0);

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           i_min_z : in  STD_LOGIC_VECTOR (3 downto 0);

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           i_min_e : in  STD_LOGIC_VECTOR (3 downto 0);

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           i_sec_z : in  STD_LOGIC_VECTOR (3 downto 0);

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           i_sec_e : in  STD_LOGIC_VECTOR (3 downto 0));

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end Digitaluhr;

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architecture Behavioral of Digitaluhr is

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     signal s_std_z :  STD_LOGIC_VECTOR (3 downto 0) := "0000";

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     signal s_std_e :  STD_LOGIC_VECTOR (3 downto 0) := "0000";

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     signal s_min_z :  STD_LOGIC_VECTOR (3 downto 0) := "0000";

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     signal s_min_e :  STD_LOGIC_VECTOR (3 downto 0) := "0000";

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     signal s_sec_z :  STD_LOGIC_VECTOR (3 downto 0) := "0000";

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     signal s_sec_e :  STD_LOGIC_VECTOR (3 downto 0) := "0000";

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begin

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--

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--test: process(i_sec_e,i_sec_z,i_min_e,i_min_z,i_std_e,i_std_z)

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--begin

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--    s_sec_e <= i_sec_e;

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--    s_sec_z <= i_sec_z;

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--    s_min_e <= i_min_e;

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--    s_min_z <= i_min_z;

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--    s_std_e <= i_std_e;

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--    s_std_z <= i_std_z;

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--    

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--end process test;

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modul: process(clk,reset)

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  begin

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  if ( reset = '1') then

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    s_std_z <= "0000";

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    s_std_e <= "0000";

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    s_min_z <= "0000";

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    s_min_e <= "0000";

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    s_sec_z <= "0000";

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    s_sec_e <= "0000";

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  end if;

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  if(clk'event and clk ='1' and mode = "00") then

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    s_sec_e <= STD_LOGIC_VECTOR(unsigned(s_sec_e)+1);

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    if(s_sec_e = "1001") then

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      s_sec_e <= "0000";

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      s_sec_z <= STD_LOGIC_VECTOR(unsigned(s_sec_z)+1);

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          if(s_sec_z = "0101" ) then

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            s_sec_z <= "0000";

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            s_min_e <= STD_LOGIC_VECTOR(unsigned(s_min_e)+1);

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              if(s_min_e = "1001") then

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                s_min_e <= "0000";

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                s_min_z <= STD_LOGIC_VECTOR(unsigned(s_min_z)+1);

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                  if(s_min_z = "0101") then

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                    s_min_z <= "0000";

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                    s_std_e <= STD_LOGIC_VECTOR(unsigned(s_std_e)+1);

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                      if(s_std_e = "1001" ) then

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                        s_std_e <= "0000";

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                        s_std_z <= STD_LOGIC_VECTOR(unsigned(s_std_z)+1);

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                      end if;

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                      if(stunde = '0') then

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                        if(s_std_z = "0001" and s_std_e = "0010") then

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                          s_std_e <= "0000";

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                          s_std_z <= "0000";

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                        end if;

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                      end if;

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                      if(stunde = '1') then

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                        if(s_std_z = "0010" and s_std_e = "0100") then

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                              s_std_e <= "0000";

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                              s_std_z <= "0000";

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                        end if;

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                      end if;

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                  end if;

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              end if;

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          end if;

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      end if;

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    end if;

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--  if(clk'event and clk ='1' and mode = "00") then

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--    s_sec_e <= STD_LOGIC_VECTOR(unsigned(s_sec_e)+1);

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--    if(s_sec_e = "1001") then

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--      s_sec_e <= "0000";

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--      s_sec_z <= STD_LOGIC_VECTOR(unsigned(s_sec_z)+1);

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--    end if;

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--    if(s_sec_z = "0101" and s_sec_e = "1001" ) then

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--      s_sec_e <= "0000";

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--      s_sec_z <= "0000";

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--      s_min_e <= STD_LOGIC_VECTOR(unsigned(s_min_e)+1);

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--    end if;

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--    if(s_min_e = "1001" and s_sec_z = "0101" and s_sec_e = "1001") then

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--      s_sec_e <= "0000";

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--      s_sec_z <= "0000";

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--      s_min_e <= "0000";

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--      s_min_z <= STD_LOGIC_VECTOR(unsigned(s_min_z)+1);

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--    end if;

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--    if(s_min_z = "0101" and s_min_e = "1001" and s_sec_z = "0101" and s_sec_e = "1001") then

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--      s_sec_e <= "0000";

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--      s_sec_z <= "0000";

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--      s_min_e <= "0000";

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--      s_min_z <= "0000";

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--      s_std_e <= STD_LOGIC_VECTOR(unsigned(s_std_e)+1);

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--    end if;

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--    if(s_std_e = "1001" and s_min_z = "0101" and s_min_e = "1001" and s_sec_z = "0101" and s_sec_e = "1001") then

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--      s_sec_e <= "0000";

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--      s_sec_z <= "0000";

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--      s_min_e <= "0000";

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--      s_min_z <= "0000";

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--      s_std_e <= "0000";

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--      s_std_z <= STD_LOGIC_VECTOR(unsigned(s_std_z)+1);

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--    end if;

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--    if(stunde = '0') then

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--      if(s_std_z = "0001" and s_std_e = "0010" and s_min_z = "0101" and s_min_e = "1001" and s_sec_z = "0101" and s_sec_e = "1001") then

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--        s_sec_e <= "0000";

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--        s_sec_z <= "0000";

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--        s_min_e <= "0000";

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--        s_min_z <= "0000";

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--        s_std_e <= "0000";

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--        s_std_z <= "0000";

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--      end if;

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--    end if;

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--    if(stunde = '1') then

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--      if(s_std_z = "0010" and s_std_e = "0100" and s_min_z = "0101" and s_min_e = "1001" and s_sec_z = "0101" and s_sec_e = "1001") then

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--        s_sec_e <= "0000";

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--        s_sec_z <= "0000";

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--        s_min_e <= "0000";

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--        s_min_z <= "0000";

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--        s_std_e <= "0000";

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--        s_std_z <= "0000";

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--      end if;

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--    

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--    end if;

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--  end if;

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--  if(clk'event and clk ='1' and mode = "01") then

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--

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--    s_sec_e <= STD_LOGIC_VECTOR(unsigned(s_sec_e)+1);

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--    if(s_sec_e = "1001") then

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--      s_sec_e <= "0000";

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--      s_sec_z <= STD_LOGIC_VECTOR(unsigned(s_sec_z)+1);

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--    end if;

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--    if(s_sec_z = "0101" and s_sec_e = "1001" ) then

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--      s_sec_e <= "0000";

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--      s_sec_z <= "0000";

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--      s_min_e <= STD_LOGIC_VECTOR(unsigned(s_min_e)+1);

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--    end if;

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--    if(s_min_e = "1001" and s_sec_z = "0101" and s_sec_e = "1001") then

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--      s_sec_e <= "0000";

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--      s_sec_z <= "0000";

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--      s_min_e <= "0000";

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--      s_min_z <= STD_LOGIC_VECTOR(unsigned(s_min_z)+1);

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--    end if;

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--    if(s_min_z = "0101" and s_min_e = "1001" and s_sec_z = "0101" and s_sec_e = "1001") then

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--      s_sec_e <= "0000";

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--      s_sec_z <= "0000";

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--      s_min_e <= "0000";

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--      s_min_z <= "0000";

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--      s_std_e <= STD_LOGIC_VECTOR(unsigned(s_std_e)+1);

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--    end if;

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--    if(s_std_e = "1001" and s_min_z = "0101" and s_min_e = "1001" and s_sec_z = "0101" and s_sec_e = "1001") then

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--      s_sec_e <= "0000";

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--      s_sec_z <= "0000";

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--      s_min_e <= "0000";

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--      s_min_z <= "0000";

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--      s_std_e <= "0000";

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--      s_std_z <= STD_LOGIC_VECTOR(unsigned(s_std_z)+1);

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--    end if;

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--

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--  end if;

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  if(clk'event and clk ='1' and mode = "01") then

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    s_sec_e <= STD_LOGIC_VECTOR(unsigned(s_sec_e)+1);

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    if(s_sec_e = "1001") then

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      s_sec_e <= "0000";

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      s_sec_z <= STD_LOGIC_VECTOR(unsigned(s_sec_z)+1);

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          if(s_sec_z = "0101" ) then

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            s_sec_z <= "0000";

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            s_min_e <= STD_LOGIC_VECTOR(unsigned(s_min_e)+1);

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              if(s_min_e = "1001") then

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                s_min_e <= "0000";

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                s_min_z <= STD_LOGIC_VECTOR(unsigned(s_min_z)+1);

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                  if(s_min_z = "0101") then

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                    s_min_z <= "0000";

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                    s_std_e <= STD_LOGIC_VECTOR(unsigned(s_std_e)+1);

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                      if(s_std_e = "1001" ) then

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                        s_std_e <= "0000";

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                        s_std_z <= STD_LOGIC_VECTOR(unsigned(s_std_z)+1);

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                      end if;

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                  end if;

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              end if;

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          end if;

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      end if;

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    end if;

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  if(clk'event and clk ='1' and mode = "10") then

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    if( s_std_z > "0000" or s_std_e > "0000" or s_min_z > "0000" or s_min_e > "0000" or s_sec_z > "0000" or s_sec_e > "0000") then

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      s_sec_e <= STD_LOGIC_VECTOR(unsigned(s_sec_e)-1);

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    end if;

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    if(s_std_z > "0000") then

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      if(s_sec_e ="0000" and s_sec_z = "0000" and s_min_e = "0000" and s_min_z = "0000" and s_std_e = "0000") then

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        s_sec_e <= "1001";

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        s_sec_z <= "0101";

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        s_min_e <= "1001";

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        s_min_z <= "0101";

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        s_std_e <= "1001";

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        s_std_z <= STD_LOGIC_VECTOR(unsigned(s_std_z)-1);

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      end if;

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    end if;

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    if(s_std_e > "0000") then

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        if(s_sec_e ="0000" and s_sec_z = "0000" and s_min_e = "0000" and s_min_z = "0000") then

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          s_sec_e <= "1001";

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          s_sec_z <= "0101";

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          s_min_e <= "1001";

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          s_min_z <= "0101";

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          s_std_e <= STD_LOGIC_VECTOR(unsigned(s_std_e)-1);

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        end if;

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    end if;

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    if(s_min_z > "0000") then

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      if(s_sec_e ="0000" and s_sec_z = "0000" and s_min_e = "0000") then

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        s_sec_e <= "1001";

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        s_sec_z <= "0101";

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        s_min_e <= "1001";

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        s_min_z <= STD_LOGIC_VECTOR(unsigned(s_min_z)-1);

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      end if;

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    end if;

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    if(s_min_e >"0000") then

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      if(s_sec_e ="0000" and s_sec_z = "0000") then

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        s_sec_e <= "1001";

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        s_sec_z <= "0101";

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        s_min_e <= STD_LOGIC_VECTOR(unsigned(s_min_e)-1);

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      end if;

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    end if;

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    if(s_sec_z >"0000") then

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      if(s_sec_e ="0000") then

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        s_sec_e <= "1001";

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        s_sec_z <= STD_LOGIC_VECTOR(unsigned(s_sec_z)-1);

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      end if;

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    end if;

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  end if;

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end process modul;

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o_sec_e <= s_sec_e;

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o_sec_z <= s_sec_z;

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o_min_e <= s_min_e;

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o_min_z <= s_min_z;

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o_std_e <= s_std_e;

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o_std_z <= s_std_z;

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end Behavioral;