Testbench-Digitaluhr.vhd

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-- Company: 

-- Engineer:

--

-- Create Date:   22:03:08 12/16/2014

-- Design Name:   

-- Module Name:   Z:/Documents/VHDL/Praktikum5_Albers-Wallner/Testbench-Digitaluhr.vhd

-- Project Name:  Praktikum5_Albers-Wallner

-- Target Device:  

-- Tool versions:  

-- Description:   

-- 

-- VHDL Test Bench Created by ISE for module: Digitaluhr

-- 

-- Dependencies:

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes: 

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test.  Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation 

-- simulation model.

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY Testbench_Digitaluhr IS

END Testbench_Digitaluhr;

ARCHITECTURE behavior OF Testbench_Digitaluhr IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Digitaluhr

    PORT(

         clk : IN  std_logic;

         reset : IN  std_logic;

         stunde : IN  std_logic;

         mode : IN  std_logic_vector(1 downto 0);

         o_std_z : OUT  std_logic_vector(3 downto 0);

         o_std_e : OUT  std_logic_vector(3 downto 0);

         o_min_z : OUT  std_logic_vector(3 downto 0);

         o_min_e : OUT  std_logic_vector(3 downto 0);

         o_sec_z : OUT  std_logic_vector(3 downto 0);

         o_sec_e : OUT  std_logic_vector(3 downto 0);

         i_std_z : IN  std_logic_vector(3 downto 0);

         i_std_e : IN  std_logic_vector(3 downto 0);

         i_min_z : IN  std_logic_vector(3 downto 0);

         i_min_e : IN  std_logic_vector(3 downto 0);

         i_sec_z : IN  std_logic_vector(3 downto 0);

         i_sec_e : IN  std_logic_vector(3 downto 0)

        );

    END COMPONENT;

   --Inputs

   signal clk : std_logic := '0';

   signal reset : std_logic := '0';

   signal stunde : std_logic := '0';

   signal mode : std_logic_vector(1 downto 0) := (others => '0');

   signal i_std_z : std_logic_vector(3 downto 0) := (others => '0');

   signal i_std_e : std_logic_vector(3 downto 0) := (others => '0');

   signal i_min_z : std_logic_vector(3 downto 0) := (others => '0');

   signal i_min_e : std_logic_vector(3 downto 0) := (others => '0');

   signal i_sec_z : std_logic_vector(3 downto 0) := (others => '0');

   signal i_sec_e : std_logic_vector(3 downto 0) := (others => '0');

   --Outputs

   signal o_std_z : std_logic_vector(3 downto 0);

   signal o_std_e : std_logic_vector(3 downto 0);

   signal o_min_z : std_logic_vector(3 downto 0);

   signal o_min_e : std_logic_vector(3 downto 0);

   signal o_sec_z : std_logic_vector(3 downto 0);

   signal o_sec_e : std_logic_vector(3 downto 0);

   -- Clock period definitions

   constant clk_period : time := 1 ns;

BEGIN

  -- Instantiate the Unit Under Test (UUT)

   uut: Digitaluhr PORT MAP (

          clk => clk,

          reset => reset,

          stunde => stunde,

          mode => mode,

          o_std_z => o_std_z,

          o_std_e => o_std_e,

          o_min_z => o_min_z,

          o_min_e => o_min_e,

          o_sec_z => o_sec_z,

          o_sec_e => o_sec_e,

          i_std_z => i_std_z,

          i_std_e => i_std_e,

          i_min_z => i_min_z,

          i_min_e => i_min_e,

          i_sec_z => i_sec_z,

          i_sec_e => i_sec_e

        );

   -- Clock process definitions

   clk_process :process

   begin

    clk <= '0';

    wait for clk_period/2;

    clk <= '1';

    wait for clk_period/2;

   end process;

   -- Stimulus process

   stim_proc: process

   begin    

      -- hold reset state for 100 ns.

  --    wait for 100 ns;  

      -- wait for clk_period*10;

      -- insert stimulus here 

  --  reset <= '0';

    mode <= "01";

    stunde <= '0';

    i_sec_e <= "0010"; 

    i_sec_z <= "0001";

    i_min_e <= "0100";

    i_min_z <= "0010";

    i_std_e <= "0100";

    i_std_z <= "0000";

      wait;

   end process;

END;