1 | ----------------------------------------------------------------------------------
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2 | -- Company:
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3 | -- Engineer:
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4 | --
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5 | -- Create Date: 12:50:24 01/04/2015
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6 | -- Design Name:
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7 | -- Module Name: DU_Code - Behavioral
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8 | -- Project Name:
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9 | -- Target Devices:
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10 | -- Tool versions:
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11 | -- Description:
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12 | --
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13 | -- Dependencies:
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14 | --
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15 | -- Revision:
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16 | -- Revision 0.01 - File Created
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17 | -- Additional Comments:
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18 | --
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19 | ----------------------------------------------------------------------------------
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20 | library IEEE;
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21 | use IEEE.STD_LOGIC_1164.ALL;
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22 | use IEEE.STD_LOGIC_unsigned.ALL;
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23 |
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24 | -- Uncomment the following library declaration if using
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25 | -- arithmetic functions with Signed or Unsigned values
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26 | use IEEE.NUMERIC_STD.ALL;
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27 |
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28 | -- Uncomment the following library declaration if instantiating
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29 | -- any Xilinx primitives in this code.
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30 | --library UNISIM;
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31 | --use UNISIM.VComponents.all;
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32 |
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33 | entity DU_Code is
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34 | Port ( clk : in STD_LOGIC;
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35 | set_time : in STD_LOGIC;
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36 | stunde : in STD_LOGIC;
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37 | mode : in STD_LOGIC_VECTOR (1 downto 0);
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38 | o_std_z : out STD_LOGIC_VECTOR (3 downto 0);
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39 | o_std_e : out STD_LOGIC_VECTOR (3 downto 0);
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40 | o_min_z : out STD_LOGIC_VECTOR (3 downto 0);
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41 | o_min_e : out STD_LOGIC_VECTOR (3 downto 0);
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42 | o_sec_z : out STD_LOGIC_VECTOR (3 downto 0);
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43 | o_sec_e : out STD_LOGIC_VECTOR (3 downto 0);
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44 | i_std_z : in STD_LOGIC_VECTOR (3 downto 0);
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45 | i_std_e : in STD_LOGIC_VECTOR (3 downto 0);
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46 | i_min_z : in STD_LOGIC_VECTOR (3 downto 0);
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47 | i_min_e : in STD_LOGIC_VECTOR (3 downto 0);
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48 | i_sec_z : in STD_LOGIC_VECTOR (3 downto 0);
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49 | i_sec_e : in STD_LOGIC_VECTOR (3 downto 0));
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50 | end DU_Code;
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51 |
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52 | architecture Behavioral of DU_Code is
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53 |
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54 | signal s_std_z : STD_LOGIC_VECTOR (3 downto 0):= "0000";
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55 | signal s_std_e : STD_LOGIC_VECTOR (3 downto 0):= "0000";
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56 | signal s_min_z : STD_LOGIC_VECTOR (3 downto 0):= "0000";
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57 | signal s_min_e : STD_LOGIC_VECTOR (3 downto 0):= "0000";
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58 | signal s_sec_z : STD_LOGIC_VECTOR (3 downto 0):= "0000";
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59 | signal s_sec_e : STD_LOGIC_VECTOR (3 downto 0):= "0000";
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60 |
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61 | begin
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62 |
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63 | modul: process begin
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64 | wait until rising_edge(clk);
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65 |
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66 |
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67 | if(mode = "00") then
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68 | s_sec_e <= STD_LOGIC_VECTOR(unsigned(s_sec_e)+1);
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69 | if(s_sec_e =9) then
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70 | s_sec_e <= "0000";
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71 | s_sec_z <= STD_LOGIC_VECTOR(unsigned(s_sec_z)+1);
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72 | end if;
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73 | if(s_sec_z = 5 and s_sec_e = 9 ) then
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74 | s_sec_e <= "0000";
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75 | s_sec_z <= "0000";
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76 | s_min_e <= STD_LOGIC_VECTOR(unsigned(s_min_e)+1);
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77 | end if;
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78 | if(s_min_e = 9 and s_sec_z =5 and s_sec_e = 9) then
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79 | s_sec_e <= "0000";
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80 | s_sec_z <= "0000";
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81 | s_min_e <= "0000";
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82 | s_min_z <= STD_LOGIC_VECTOR(unsigned(s_min_z)+1);
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83 | end if;
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84 | if(s_min_z = 5 and s_min_e = 9 and s_sec_z =5 and s_sec_e = 9) then
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85 | s_sec_e <= "0000";
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86 | s_sec_z <= "0000";
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87 | s_min_e <= "0000";
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88 | s_min_z <= "0000";
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89 | s_std_e <= STD_LOGIC_VECTOR(unsigned(s_std_e)+1);
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90 | end if;
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91 | if(s_std_e = 9 and s_min_z = 5 and s_min_e = 9 and s_sec_z = 5 and s_sec_e = 9) then
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92 | s_sec_e <= "0000";
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93 | s_sec_z <= "0000";
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94 | s_min_e <= "0000";
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95 | s_min_z <= "0000";
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96 | s_std_e <= "0000";
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97 | s_std_z <= STD_LOGIC_VECTOR(unsigned(s_std_z)+1);
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98 | end if;
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99 | if(stunde = '0') then
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100 | if(s_std_z = 1 and s_std_e = 2 and s_min_z = 5 and s_min_e = 9 and s_sec_z = 5 and s_sec_e = 9) then
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101 | s_sec_e <= "0000";
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102 | s_sec_z <= "0000";
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103 | s_min_e <= "0000";
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104 | s_min_z <= "0000";
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105 | s_std_e <= "0000";
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106 | s_std_z <= "0000";
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107 | end if;
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108 | end if;
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109 | if(stunde = '1') then
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110 | if(s_std_z = 2 and s_std_e = 4 and s_min_z = 5 and s_min_e = 9 and s_sec_z = 5 and s_sec_e = 9) then
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111 | s_sec_e <= "0000";
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112 | s_sec_z <= "0000";
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113 | s_min_e <= "0000";
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114 | s_min_z <= "0000";
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115 | s_std_e <= "0000";
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116 | s_std_z <= "0000";
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117 | end if;
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118 |
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119 | end if;
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120 | end if;
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121 |
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122 | if(mode = "01") then
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123 |
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124 | s_sec_e <= STD_LOGIC_VECTOR(unsigned(s_sec_e)+1);
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125 | if(s_sec_e = 9) then
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126 | s_sec_e <= "0000";
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127 | s_sec_z <= STD_LOGIC_VECTOR(unsigned(s_sec_z)+1);
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128 | end if;
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129 | if(s_sec_z = 5 and s_sec_e = 9 ) then
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130 | s_sec_e <= "0000";
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131 | s_sec_z <= "0000";
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132 | s_min_e <= STD_LOGIC_VECTOR(unsigned(s_min_e)+1);
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133 | end if;
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134 | if(s_min_e = 9 and s_sec_z = 5 and s_sec_e = 9) then
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135 | s_sec_e <= "0000";
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136 | s_sec_z <= "0000";
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137 | s_min_e <= "0000";
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138 | s_min_z <= STD_LOGIC_VECTOR(unsigned(s_min_z)+1);
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139 | end if;
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140 | if(s_min_z = 5 and s_min_e = 9 and s_sec_z = 5 and s_sec_e = 9) then
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141 | s_sec_e <= "0000";
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142 | s_sec_z <= "0000";
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143 | s_min_e <= "0000";
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144 | s_min_z <= "0000";
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145 | s_std_e <= STD_LOGIC_VECTOR(unsigned(s_std_e)+1);
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146 | end if;
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147 | if(s_std_e = 9 and s_min_z = 5 and s_min_e = 9 and s_sec_z = 5 and s_sec_e = 9) then
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148 | s_sec_e <= "0000";
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149 | s_sec_z <= "0000";
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150 | s_min_e <= "0000";
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151 | s_min_z <= "0000";
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152 | s_std_e <= "0000";
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153 | s_std_z <= STD_LOGIC_VECTOR(unsigned(s_std_z)+1);
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154 | end if;
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155 |
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156 | end if;
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157 |
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158 |
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159 | if(mode = "10") then
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160 | if( s_std_z > 0 or s_std_e > 0 or s_min_z > 0 or s_min_e > 0 or s_sec_z > 0 or s_sec_e > 0) then
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161 | s_sec_e <= STD_LOGIC_VECTOR(unsigned(s_sec_e)-1);
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162 | end if;
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163 |
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164 | if(s_std_z > 0) then
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165 | if(s_sec_e =0 and s_sec_z = 0 and s_min_e = 0 and s_min_z = 0 and s_std_e = 0) then
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166 | s_sec_e <= "1001";
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167 | s_sec_z <= "0101";
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168 | s_min_e <= "1001";
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169 | s_min_z <= "0101";
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170 | s_std_e <= "1001";
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171 | s_std_z <= STD_LOGIC_VECTOR(unsigned(s_std_z)-1);
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172 | end if;
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173 | end if;
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174 |
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175 | if(s_std_e > 0) then
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176 | if(s_sec_e =0 and s_sec_z = 0 and s_min_e = 0 and s_min_z = 0) then
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177 | s_sec_e <= "1001";
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178 | s_sec_z <= "0101";
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179 | s_min_e <= "1001";
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180 | s_min_z <= "0101";
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181 | s_std_e <= STD_LOGIC_VECTOR(unsigned(s_std_e)-1);
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182 | end if;
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183 | end if;
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184 |
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185 | if(s_min_z > 0) then
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186 | if(s_sec_e =0 and s_sec_z = 0 and s_min_e = 0) then
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187 | s_sec_e <= "1001";
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188 | s_sec_z <= "0101";
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189 | s_min_e <= "1001";
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190 | s_min_z <= STD_LOGIC_VECTOR(unsigned(s_min_z)-1);
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191 | end if;
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192 | end if;
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193 |
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194 | if(s_min_e >0) then
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195 | if(s_sec_e =0 and s_sec_z = 0) then
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196 | s_sec_e <= "1001";
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197 | s_sec_z <= "0101";
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198 | s_min_e <= STD_LOGIC_VECTOR(unsigned(s_min_e)-1);
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199 | end if;
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200 | end if;
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201 |
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202 | if(s_sec_z >0) then
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203 | if(s_sec_e =0) then
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204 | s_sec_e <= "1001";
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205 | s_sec_z <= STD_LOGIC_VECTOR(unsigned(s_sec_z)-1);
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206 | end if;
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207 | end if;
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208 |
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209 | end if;
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210 |
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211 | if (set_time='1') then
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212 | s_sec_e <= i_sec_e;
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213 | s_sec_z <= i_sec_z;
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214 | s_min_e <= i_min_e;
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215 | s_min_z <= i_min_z;
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216 | s_std_e <= i_std_e;
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217 | s_std_z <= i_std_z;
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218 | end if;
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219 |
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220 |
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221 | end process modul;
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222 |
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223 | o_sec_e <= s_sec_e;
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224 | o_sec_z <= s_sec_z;
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225 | o_min_e <= s_min_e;
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226 | o_min_z <= s_min_z;
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227 | o_std_e <= s_std_e;
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228 | o_std_z <= s_std_z;
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229 |
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230 |
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231 | end Behavioral;
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