DU_Testbench.vhd

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-- Company: 

-- Engineer:

--

-- Create Date:   12:56:41 01/04/2015

-- Design Name:   

-- Module Name:   Z:/Documents/VHDL/Digitaluhr_5_Neu/DU_Testbench.vhd

-- Project Name:  Digitaluhr_5_Neu

-- Target Device:  

-- Tool versions:  

-- Description:   

-- 

-- VHDL Test Bench Created by ISE for module: DU_Code

-- 

-- Dependencies:

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes: 

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test.  Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation 

-- simulation model.

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY DU_Testbench IS

END DU_Testbench;

ARCHITECTURE behavior OF DU_Testbench IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT DU_Code

    PORT(

         clk : IN  std_logic;

         set_time : IN  std_logic;

         stunde : IN  std_logic;

         mode : IN  std_logic_vector(1 downto 0);

         o_std_z : OUT  std_logic_vector(3 downto 0);

         o_std_e : OUT  std_logic_vector(3 downto 0);

         o_min_z : OUT  std_logic_vector(3 downto 0);

         o_min_e : OUT  std_logic_vector(3 downto 0);

         o_sec_z : OUT  std_logic_vector(3 downto 0);

         o_sec_e : OUT  std_logic_vector(3 downto 0);

         i_std_z : IN  std_logic_vector(3 downto 0);

         i_std_e : IN  std_logic_vector(3 downto 0);

         i_min_z : IN  std_logic_vector(3 downto 0);

         i_min_e : IN  std_logic_vector(3 downto 0);

         i_sec_z : IN  std_logic_vector(3 downto 0);

         i_sec_e : IN  std_logic_vector(3 downto 0)

        );

    END COMPONENT;

   --Inputs

   signal clk : std_logic := '0';

   signal set_time : std_logic := '0';

   signal stunde : std_logic := '0';

   signal mode : std_logic_vector(1 downto 0) := (others => '0');

   signal i_std_z : std_logic_vector(3 downto 0) := (others => '0');

   signal i_std_e : std_logic_vector(3 downto 0) := (others => '0');

   signal i_min_z : std_logic_vector(3 downto 0) := (others => '0');

   signal i_min_e : std_logic_vector(3 downto 0) := (others => '0');

   signal i_sec_z : std_logic_vector(3 downto 0) := (others => '0');

   signal i_sec_e : std_logic_vector(3 downto 0) := (others => '0');

   --Outputs

   signal o_std_z : std_logic_vector(3 downto 0);

   signal o_std_e : std_logic_vector(3 downto 0);

   signal o_min_z : std_logic_vector(3 downto 0);

   signal o_min_e : std_logic_vector(3 downto 0);

   signal o_sec_z : std_logic_vector(3 downto 0);

   signal o_sec_e : std_logic_vector(3 downto 0);

   -- Clock period definitions

   constant clk_period : time := 1 ns;

BEGIN

  -- Instantiate the Unit Under Test (UUT)

   uut: DU_Code PORT MAP (

          clk => clk,

          set_time => set_time,

          stunde => stunde,

          mode => mode,

          o_std_z => o_std_z,

          o_std_e => o_std_e,

          o_min_z => o_min_z,

          o_min_e => o_min_e,

          o_sec_z => o_sec_z,

          o_sec_e => o_sec_e,

          i_std_z => i_std_z,

          i_std_e => i_std_e,

          i_min_z => i_min_z,

          i_min_e => i_min_e,

          i_sec_z => i_sec_z,

          i_sec_e => i_sec_e

        );

   -- Clock process definitions

   clk_process :process

   begin

    clk <= '0';

    wait for clk_period/2;

    clk <= '1';

    wait for clk_period/2;

   end process;

   -- Stimulus process

   stim_proc: process

   begin    

      -- hold reset state for 100 ns.

   --   wait for 100 ns;  

      wait for clk_period*10;

      -- insert stimulus here 

    set_time <= '1', '0' after 50 ns;

    if (set_time = '1') then

      i_sec_e <= "0010"; 

      i_sec_z <= "0001";

      i_min_e <= "0100";

      i_min_z <= "0010";

      i_std_e <= "0100";

      i_std_z <= "0000";

    end if;

    stunde <= '0' after 50 ns;

    mode <= "01" after 50 ns;

      wait;

   end process;

END;