1 | /**
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2 | ******************************************************************************
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3 | * @file stm32f4x7_eth.c
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4 | * @author MCD Application Team
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5 | * @version V1.0.0
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6 | * @date 14-October-2011
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7 | * @brief This file is the low level driver for STM32F407xx/417xx Ethernet Controller.
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8 | * This driver does not include low level functions for PTP time-stamp.
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9 | ******************************************************************************
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10 | * @attention
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11 | *
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12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 | *
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19 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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20 | ******************************************************************************
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21 | */
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22 |
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23 |
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24 | /*-----------------------------------------------------------------------*/
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25 | /* Angepasst von UB */
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26 | /* V:1.0 / 10.05.2013 */
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27 | /*-----------------------------------------------------------------------*/
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28 |
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29 | /* Includes ------------------------------------------------------------------*/
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30 | #include "stm32f4x7_eth.h"
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31 | #include "stm32f4xx_rcc.h"
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32 | #include <string.h>
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33 |
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34 | /** @addtogroup STM32F4x7_ETH_Driver
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35 | * @brief ETH driver modules
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36 | * @{
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37 | */
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38 |
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39 | /** @defgroup ETH_Private_TypesDefinitions
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40 | * @{
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41 | */
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42 | /**
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43 | * @}
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44 | */
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45 |
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46 |
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47 | /** @defgroup ETH_Private_Defines
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48 | * @{
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49 | */
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50 |
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51 | /**
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52 | * @}
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53 | */
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54 |
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55 | /** @defgroup ETH_Private_Macros
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56 | * @{
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57 | */
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58 | /**
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59 | * @}
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60 | */
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61 |
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62 | /** @defgroup ETH_Private_Variables
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63 | * @{
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64 | */
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65 |
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66 | #if defined (__CC_ARM) /*!< ARM Compiler */
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67 | __align(4)
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68 | ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB];/* Ethernet Rx MA Descriptor */
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69 | __align(4)
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70 | ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB];/* Ethernet Tx DMA Descriptor */
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71 | __align(4)
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72 | uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /* Ethernet Receive Buffer */
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73 | __align(4)
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74 | uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /* Ethernet Transmit Buffer */
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75 |
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76 | #elif defined ( __ICCARM__ ) /*!< IAR Compiler */
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77 | #pragma data_alignment=4
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78 | ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB];/* Ethernet Rx MA Descriptor */
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79 | #pragma data_alignment=4
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80 | ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB];/* Ethernet Tx DMA Descriptor */
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81 | #pragma data_alignment=4
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82 | uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /* Ethernet Receive Buffer */
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83 | #pragma data_alignment=4
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84 | uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /* Ethernet Transmit Buffer */
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85 |
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86 | #elif defined (__GNUC__) /*!< GNU Compiler */
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87 | ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB] __attribute__ ((aligned (4))); /* Ethernet Rx DMA Descriptor */
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88 | ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB] __attribute__ ((aligned (4))); /* Ethernet Tx DMA Descriptor */
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89 | uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__ ((aligned (4))); /* Ethernet Receive Buffer */
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90 | uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__ ((aligned (4))); /* Ethernet Transmit Buffer */
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91 |
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92 | #elif defined (__TASKING__) /*!< TASKING Compiler */
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93 | __align(4)
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94 | ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB];/* Ethernet Rx MA Descriptor */
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95 | __align(4)
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96 | ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB];/* Ethernet Tx DMA Descriptor */
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97 | __align(4)
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98 | uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /* Ethernet Receive Buffer */
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99 | __align(4)
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100 | uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /* Ethernet Transmit Buffer */
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101 |
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102 | #endif /* __CC_ARM */
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103 |
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104 |
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105 | /* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
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106 | volatile ETH_DMADESCTypeDef *DMATxDescToSet;
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107 | volatile ETH_DMADESCTypeDef *DMARxDescToGet;
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108 |
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109 |
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110 | /* Structure used to hold the last received packet descriptors info */
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111 |
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112 | ETH_DMA_Rx_Frame_infos RX_Frame_Descriptor;
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113 | volatile ETH_DMA_Rx_Frame_infos *DMA_RX_FRAME_infos;
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114 | volatile uint32_t Frame_Rx_index;
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115 |
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116 |
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117 | /**
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118 | * @}
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119 | */
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120 |
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121 | /** @defgroup ETH_Private_FunctionPrototypes
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122 | * @{
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123 | */
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124 | /**
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125 | * @}
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126 | */
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127 |
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128 | /** @defgroup ETH_Private_Functions
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129 | * @{
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130 | */
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131 |
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132 | #ifndef USE_Delay
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133 | /**
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134 | * @brief Inserts a delay time.
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135 | * @param nCount: specifies the delay time length.
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136 | * @retval None
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137 | */
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138 | static void ETH_Delay(volatile uint32_t nCount)
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139 | {
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140 | volatile uint32_t index = 0;
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141 | for(index = nCount; index != 0; index--)
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142 | {
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143 | }
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144 | }
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145 | #endif /* USE_Delay*/
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146 |
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147 |
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148 |
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149 | /******************************************************************************/
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150 | /* Global ETH MAC/DMA functions */
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151 | /******************************************************************************/
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152 |
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153 | /**
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154 | * @brief Deinitializes the ETHERNET peripheral registers to their default reset values.
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155 | * @param None
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156 | * @retval None
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157 | */
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158 | void ETH_DeInit(void)
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159 | {
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160 | RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE);
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161 | RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE);
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162 | }
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163 |
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164 |
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165 | /**
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166 | * @brief Fills each ETH_InitStruct member with its default value.
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167 | * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure which will be initialized.
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168 | * @retval None
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169 | */
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170 | void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)
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171 | {
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172 | /* ETH_InitStruct members default value */
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173 | /*------------------------ MAC Configuration ---------------------------*/
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174 |
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175 | /* PHY Auto-negotiation enabled */
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176 | ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
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177 | /* MAC watchdog enabled: cuts-off long frame */
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178 | ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
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179 | /* MAC Jabber enabled in Half-duplex mode */
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180 | ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;
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181 | /* Ethernet interframe gap set to 96 bits */
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182 | ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
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183 | /* Carrier Sense Enabled in Half-Duplex mode */
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184 | ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;
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185 | /* PHY speed configured to 100Mbit/s */
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186 | ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
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187 | /* Receive own Frames in Half-Duplex mode enabled */
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188 | ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;
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189 | /* MAC MII loopback disabled */
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190 | ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;
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191 | /* Full-Duplex mode selected */
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192 | ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
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193 | /* IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled */
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194 | ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
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195 | /* Retry Transmission enabled for half-duplex mode */
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196 | ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;
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197 | /* Automatic PAD/CRC strip disabled*/
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198 | ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
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199 | /* half-duplex mode retransmission Backoff time_limit = 10 slot times*/
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200 | ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;
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201 | /* half-duplex mode Deferral check disabled */
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202 | ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;
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203 | /* Receive all frames disabled */
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204 | ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
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205 | /* Source address filtering (on the optional MAC addresses) disabled */
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206 | ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
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207 | /* Do not forward control frames that do not pass the address filtering */
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208 | ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
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209 | /* Disable reception of Broadcast frames */
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210 | ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
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211 | /* Normal Destination address filtering (not reverse addressing) */
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212 | ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
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213 | /* Promiscuous address filtering mode disabled */
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214 | ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
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215 | /* Perfect address filtering for multicast addresses */
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216 | ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
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217 | /* Perfect address filtering for unicast addresses */
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218 | ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
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219 | /* Initialize hash table high and low regs */
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220 | ETH_InitStruct->ETH_HashTableHigh = 0x0;
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221 | ETH_InitStruct->ETH_HashTableLow = 0x0;
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222 | /* Flow control config (flow control disabled)*/
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223 | ETH_InitStruct->ETH_PauseTime = 0x0;
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224 | ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
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225 | ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
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226 | ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
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227 | ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
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228 | ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
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229 | /* VLANtag config (VLAN field not checked) */
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230 | ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
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231 | ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
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232 |
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233 | /*---------------------- DMA Configuration -------------------------------*/
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234 |
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235 | /* Drops frames with with TCP/IP checksum errors */
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236 | ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
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237 | /* Store and forward mode enabled for receive */
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238 | ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
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239 | /* Flush received frame that created FIFO overflow */
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240 | ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable;
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241 | /* Store and forward mode enabled for transmit */
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242 | ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
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243 | /* Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled) */
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244 | ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
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245 | /* Disable forwarding frames with errors (short frames, CRC,...)*/
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246 | ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
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247 | /* Disable undersized good frames */
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248 | ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
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249 | /* Threshold RXFIFO level set to 64 bytes (used when Cut-through mode is enabled) */
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250 | ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
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251 | /* Disable Operate on second frame (transmit a second frame to FIFO without
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252 | waiting status of previous frame*/
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253 | ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
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254 | /* DMA works on 32-bit aligned start source and destinations addresses */
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255 | ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
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256 | /* Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions */
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257 | ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Enable;
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258 | /* DMA transfer max burst length = 32 beats = 32 x 32bits */
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259 | ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
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260 | ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
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261 | /* DMA Ring mode skip length = 0 */
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262 | ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
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263 | /* Equal priority (round-robin) between transmit and receive DMA engines */
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264 | ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
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265 | }
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266 |
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267 |
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268 | /**
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269 | * @brief Initializes the ETHERNET peripheral according to the specified
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270 | * parameters in the ETH_InitStruct .
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271 | * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains
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272 | * the configuration information for the specified ETHERNET peripheral.
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273 | * @param PHYAddress: external PHY address
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274 | * @retval ETH_ERROR: Ethernet initialization failed
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275 | * ETH_SUCCESS: Ethernet successfully initialized
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276 | */
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277 | uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
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278 | {
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279 | uint32_t RegValue = 0, tmpreg = 0;
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280 | // volatile uint32_t i = 0; // UB (wird nicht benutzt)
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281 | RCC_ClocksTypeDef rcc_clocks;
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282 | uint32_t hclk = 60000000;
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283 | volatile uint32_t timeout = 0;
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284 | /* Check the parameters */
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285 | /* MAC --------------------------*/
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286 | assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
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287 | assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
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288 | assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
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289 | assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
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290 | assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
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291 | assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
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292 | assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
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293 | assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
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294 | assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
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295 | assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
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296 | assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
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297 | assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
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298 | assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
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299 | assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
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300 | assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
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301 | assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
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302 | assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
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303 | assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
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304 | assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
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305 | assert_param(IS_ETH_PROMISCIOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
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306 | assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));
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307 | assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
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308 | assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
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309 | assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
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310 | assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
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311 | assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
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312 | assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
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313 | assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
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314 | assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
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315 | assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
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316 | /* DMA --------------------------*/
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317 | assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
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318 | assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
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319 | assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
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320 | assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
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321 | assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
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322 | assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
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323 | assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
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324 | assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
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325 | assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
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326 | assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
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327 | assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
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328 | assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
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329 | assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength));
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330 | assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));
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331 | assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));
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332 | /*-------------------------------- MAC Config ------------------------------*/
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333 | /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
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334 | /* Get the ETHERNET MACMIIAR value */
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335 | tmpreg = ETH->MACMIIAR;
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336 | /* Clear CSR Clock Range CR[2:0] bits */
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337 | tmpreg &= MACMIIAR_CR_MASK;
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338 | /* Get hclk frequency value */
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339 | RCC_GetClocksFreq(&rcc_clocks);
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340 | hclk = rcc_clocks.HCLK_Frequency;
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341 |
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342 | /* Set CR bits depending on hclk value */
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343 | if((hclk >= 20000000)&&(hclk < 35000000))
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344 | {
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345 | /* CSR Clock Range between 20-35 MHz */
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346 | tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
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347 | }
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348 | else if((hclk >= 35000000)&&(hclk < 60000000))
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349 | {
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350 | /* CSR Clock Range between 35-60 MHz */
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351 | tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
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352 | }
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353 | else if((hclk >= 60000000)&&(hclk < 100000000))
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354 | {
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355 | /* CSR Clock Range between 60-100 MHz */
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356 | tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
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357 | }
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358 | else if((hclk >= 100000000)&&(hclk < 150000000))
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359 | {
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360 | /* CSR Clock Range between 100-150 MHz */
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361 | tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
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362 | }
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363 | else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
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364 | {
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365 | /* CSR Clock Range between 150-168 MHz */
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366 | tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
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367 | }
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368 |
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369 | /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
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370 | ETH->MACMIIAR = (uint32_t)tmpreg;
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371 | /*-------------------- PHY initialization and configuration ----------------*/
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372 | /* Put the PHY in reset mode */
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373 | if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
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374 | {
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375 | /* Return ERROR in case of write timeout */
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376 | return ETH_ERROR;
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377 | }
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378 |
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379 | /* Delay to assure PHY reset */
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380 | _eth_delay_(PHY_RESET_DELAY);
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381 |
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382 | if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
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383 | {
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384 | /* We wait for linked status... */
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385 | do
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386 | {
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387 | timeout++;
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388 | } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
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389 |
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390 | /* Return ERROR in case of timeout */
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391 | if(timeout == PHY_READ_TO)
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392 | {
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393 | return ETH_ERROR;
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394 | }
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395 |
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396 | /* Reset Timeout counter */
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397 | timeout = 0;
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398 | /* Enable Auto-Negotiation */
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399 | if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
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400 | {
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401 | /* Return ERROR in case of write timeout */
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402 | return ETH_ERROR;
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403 | }
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404 |
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405 | /* Wait until the auto-negotiation will be completed */
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406 | do
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407 | {
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408 | timeout++;
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409 | } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));
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410 |
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411 | /* Return ERROR in case of timeout */
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412 | if(timeout == PHY_READ_TO)
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413 | {
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414 | return ETH_ERROR;
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415 | }
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416 |
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417 | /* Reset Timeout counter */
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418 | timeout = 0;
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419 |
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420 | /* Read the result of the auto-negotiation */
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421 | RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
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422 |
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423 | /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
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424 | if((RegValue & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
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425 | {
|
426 | /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
|
427 | ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
|
428 | }
|
429 | else
|
430 | {
|
431 | /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
|
432 | ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
|
433 | }
|
434 |
|
435 | /* Configure the MAC with the speed fixed by the auto-negotiation process */
|
436 | if(RegValue & PHY_SPEED_STATUS)
|
437 | {
|
438 | /* Set Ethernet speed to 10M following the auto-negotiation */
|
439 | ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
|
440 | }
|
441 | else
|
442 | {
|
443 | /* Set Ethernet speed to 100M following the auto-negotiation */
|
444 | ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
|
445 | }
|
446 | }
|
447 | else
|
448 | {
|
449 | if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
|
450 | (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))
|
451 | {
|
452 | /* Return ERROR in case of write timeout */
|
453 | return ETH_ERROR;
|
454 | }
|
455 | /* Delay to assure PHY configuration */
|
456 | _eth_delay_(PHY_CONFIG_DELAY);
|
457 |
|
458 | }
|
459 | /*------------------------ ETHERNET MACCR Configuration --------------------*/
|
460 | /* Get the ETHERNET MACCR value */
|
461 | tmpreg = ETH->MACCR;
|
462 | /* Clear WD, PCE, PS, TE and RE bits */
|
463 | tmpreg &= MACCR_CLEAR_MASK;
|
464 | /* Set the WD bit according to ETH_Watchdog value */
|
465 | /* Set the JD: bit according to ETH_Jabber value */
|
466 | /* Set the IFG bit according to ETH_InterFrameGap value */
|
467 | /* Set the DCRS bit according to ETH_CarrierSense value */
|
468 | /* Set the FES bit according to ETH_Speed value */
|
469 | /* Set the DO bit according to ETH_ReceiveOwn value */
|
470 | /* Set the LM bit according to ETH_LoopbackMode value */
|
471 | /* Set the DM bit according to ETH_Mode value */
|
472 | /* Set the IPCO bit according to ETH_ChecksumOffload value */
|
473 | /* Set the DR bit according to ETH_RetryTransmission value */
|
474 | /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
|
475 | /* Set the BL bit according to ETH_BackOffLimit value */
|
476 | /* Set the DC bit according to ETH_DeferralCheck value */
|
477 | tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog |
|
478 | ETH_InitStruct->ETH_Jabber |
|
479 | ETH_InitStruct->ETH_InterFrameGap |
|
480 | ETH_InitStruct->ETH_CarrierSense |
|
481 | ETH_InitStruct->ETH_Speed |
|
482 | ETH_InitStruct->ETH_ReceiveOwn |
|
483 | ETH_InitStruct->ETH_LoopbackMode |
|
484 | ETH_InitStruct->ETH_Mode |
|
485 | ETH_InitStruct->ETH_ChecksumOffload |
|
486 | ETH_InitStruct->ETH_RetryTransmission |
|
487 | ETH_InitStruct->ETH_AutomaticPadCRCStrip |
|
488 | ETH_InitStruct->ETH_BackOffLimit |
|
489 | ETH_InitStruct->ETH_DeferralCheck);
|
490 | /* Write to ETHERNET MACCR */
|
491 | ETH->MACCR = (uint32_t)tmpreg;
|
492 |
|
493 | /*----------------------- ETHERNET MACFFR Configuration --------------------*/
|
494 | /* Set the RA bit according to ETH_ReceiveAll value */
|
495 | /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
|
496 | /* Set the PCF bit according to ETH_PassControlFrames value */
|
497 | /* Set the DBF bit according to ETH_BroadcastFramesReception value */
|
498 | /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
|
499 | /* Set the PR bit according to ETH_PromiscuousMode value */
|
500 | /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
|
501 | /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
|
502 | /* Write to ETHERNET MACFFR */
|
503 | ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
|
504 | ETH_InitStruct->ETH_SourceAddrFilter |
|
505 | ETH_InitStruct->ETH_PassControlFrames |
|
506 | ETH_InitStruct->ETH_BroadcastFramesReception |
|
507 | ETH_InitStruct->ETH_DestinationAddrFilter |
|
508 | ETH_InitStruct->ETH_PromiscuousMode |
|
509 | ETH_InitStruct->ETH_MulticastFramesFilter |
|
510 | ETH_InitStruct->ETH_UnicastFramesFilter);
|
511 | /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
|
512 | /* Write to ETHERNET MACHTHR */
|
513 | ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
|
514 | /* Write to ETHERNET MACHTLR */
|
515 | ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
|
516 | /*----------------------- ETHERNET MACFCR Configuration --------------------*/
|
517 | /* Get the ETHERNET MACFCR value */
|
518 | tmpreg = ETH->MACFCR;
|
519 | /* Clear xx bits */
|
520 | tmpreg &= MACFCR_CLEAR_MASK;
|
521 |
|
522 | /* Set the PT bit according to ETH_PauseTime value */
|
523 | /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
|
524 | /* Set the PLT bit according to ETH_PauseLowThreshold value */
|
525 | /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
|
526 | /* Set the RFE bit according to ETH_ReceiveFlowControl value */
|
527 | /* Set the TFE bit according to ETH_TransmitFlowControl value */
|
528 | tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
|
529 | ETH_InitStruct->ETH_ZeroQuantaPause |
|
530 | ETH_InitStruct->ETH_PauseLowThreshold |
|
531 | ETH_InitStruct->ETH_UnicastPauseFrameDetect |
|
532 | ETH_InitStruct->ETH_ReceiveFlowControl |
|
533 | ETH_InitStruct->ETH_TransmitFlowControl);
|
534 | /* Write to ETHERNET MACFCR */
|
535 | ETH->MACFCR = (uint32_t)tmpreg;
|
536 | /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
|
537 | /* Set the ETV bit according to ETH_VLANTagComparison value */
|
538 | /* Set the VL bit according to ETH_VLANTagIdentifier value */
|
539 | ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
|
540 | ETH_InitStruct->ETH_VLANTagIdentifier);
|
541 |
|
542 | /*-------------------------------- DMA Config ------------------------------*/
|
543 | /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
|
544 | /* Get the ETHERNET DMAOMR value */
|
545 | tmpreg = ETH->DMAOMR;
|
546 | /* Clear xx bits */
|
547 | tmpreg &= DMAOMR_CLEAR_MASK;
|
548 |
|
549 | /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
|
550 | /* Set the RSF bit according to ETH_ReceiveStoreForward value */
|
551 | /* Set the DFF bit according to ETH_FlushReceivedFrame value */
|
552 | /* Set the TSF bit according to ETH_TransmitStoreForward value */
|
553 | /* Set the TTC bit according to ETH_TransmitThresholdControl value */
|
554 | /* Set the FEF bit according to ETH_ForwardErrorFrames value */
|
555 | /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
|
556 | /* Set the RTC bit according to ETH_ReceiveThresholdControl value */
|
557 | /* Set the OSF bit according to ETH_SecondFrameOperate value */
|
558 | tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
|
559 | ETH_InitStruct->ETH_ReceiveStoreForward |
|
560 | ETH_InitStruct->ETH_FlushReceivedFrame |
|
561 | ETH_InitStruct->ETH_TransmitStoreForward |
|
562 | ETH_InitStruct->ETH_TransmitThresholdControl |
|
563 | ETH_InitStruct->ETH_ForwardErrorFrames |
|
564 | ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
|
565 | ETH_InitStruct->ETH_ReceiveThresholdControl |
|
566 | ETH_InitStruct->ETH_SecondFrameOperate);
|
567 | /* Write to ETHERNET DMAOMR */
|
568 | ETH->DMAOMR = (uint32_t)tmpreg;
|
569 |
|
570 | /*----------------------- ETHERNET DMABMR Configuration --------------------*/
|
571 | /* Set the AAL bit according to ETH_AddressAlignedBeats value */
|
572 | /* Set the FB bit according to ETH_FixedBurst value */
|
573 | /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
|
574 | /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
|
575 | /* Set the DSL bit according to ETH_DesciptorSkipLength value */
|
576 | /* Set the PR and DA bits according to ETH_DMAArbitration value */
|
577 | ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats |
|
578 | ETH_InitStruct->ETH_FixedBurst |
|
579 | ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
|
580 | ETH_InitStruct->ETH_TxDMABurstLength |
|
581 | (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
|
582 | ETH_InitStruct->ETH_DMAArbitration |
|
583 | ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
|
584 |
|
585 | #ifdef USE_ENHANCED_DMA_DESCRIPTORS
|
586 | /* Enable the Enhanced DMA descriptors */
|
587 | ETH->DMABMR |= ETH_DMABMR_EDE;
|
588 | #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
|
589 |
|
590 | /* Return Ethernet configuration success */
|
591 | return ETH_SUCCESS;
|
592 | }
|
593 |
|
594 | /**
|
595 | * @brief Enables ENET MAC and DMA reception/transmission
|
596 | * @param None
|
597 | * @retval None
|
598 | */
|
599 | void ETH_Start(void)
|
600 | {
|
601 | /* Enable transmit state machine of the MAC for transmission on the MII */
|
602 | ETH_MACTransmissionCmd(ENABLE);
|
603 | /* Flush Transmit FIFO */
|
604 | ETH_FlushTransmitFIFO();
|
605 | /* Enable receive state machine of the MAC for reception from the MII */
|
606 | ETH_MACReceptionCmd(ENABLE);
|
607 |
|
608 | /* Start DMA transmission */
|
609 | ETH_DMATransmissionCmd(ENABLE);
|
610 | /* Start DMA reception */
|
611 | ETH_DMAReceptionCmd(ENABLE);
|
612 | }
|
613 |
|
614 | void ETH_Stop(void)
|
615 | {
|
616 | /* Stop DMA transmission */
|
617 | ETH_DMATransmissionCmd(DISABLE);
|
618 |
|
619 | /* Stop DMA reception */
|
620 | ETH_DMAReceptionCmd(DISABLE);
|
621 |
|
622 | /* Disable receive state machine of the MAC for reception from the MII */
|
623 | ETH_MACReceptionCmd(DISABLE);
|
624 |
|
625 | /* Flush Transmit FIFO */
|
626 | ETH_FlushTransmitFIFO();
|
627 |
|
628 | /* Disable transmit state machine of the MAC for transmission on the MII */
|
629 | ETH_MACTransmissionCmd(DISABLE);
|
630 | }
|
631 |
|
632 | /**
|
633 | * @brief Enables or disables the MAC transmission.
|
634 | * @param NewState: new state of the MAC transmission.
|
635 | * This parameter can be: ENABLE or DISABLE.
|
636 | * @retval None
|
637 | */
|
638 | void ETH_MACTransmissionCmd(FunctionalState NewState)
|
639 | {
|
640 | /* Check the parameters */
|
641 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
642 |
|
643 | if (NewState != DISABLE)
|
644 | {
|
645 | /* Enable the MAC transmission */
|
646 | ETH->MACCR |= ETH_MACCR_TE;
|
647 | }
|
648 | else
|
649 | {
|
650 | /* Disable the MAC transmission */
|
651 | ETH->MACCR &= ~ETH_MACCR_TE;
|
652 | }
|
653 | }
|
654 |
|
655 |
|
656 | /**
|
657 | * @brief Enables or disables the MAC reception.
|
658 | * @param NewState: new state of the MAC reception.
|
659 | * This parameter can be: ENABLE or DISABLE.
|
660 | * @retval None
|
661 | */
|
662 | void ETH_MACReceptionCmd(FunctionalState NewState)
|
663 | {
|
664 | /* Check the parameters */
|
665 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
666 |
|
667 | if (NewState != DISABLE)
|
668 | {
|
669 | /* Enable the MAC reception */
|
670 | ETH->MACCR |= ETH_MACCR_RE;
|
671 | }
|
672 | else
|
673 | {
|
674 | /* Disable the MAC reception */
|
675 | ETH->MACCR &= ~ETH_MACCR_RE;
|
676 | }
|
677 | }
|
678 |
|
679 |
|
680 | /**
|
681 | * @brief Checks whether the ETHERNET flow control busy bit is set or not.
|
682 | * @param None
|
683 | * @retval The new state of flow control busy status bit (SET or RESET).
|
684 | */
|
685 | FlagStatus ETH_GetFlowControlBusyStatus(void)
|
686 | {
|
687 | FlagStatus bitstatus = RESET;
|
688 | /* The Flow Control register should not be written to until this bit is cleared */
|
689 | if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET)
|
690 | {
|
691 | bitstatus = SET;
|
692 | }
|
693 | else
|
694 | {
|
695 | bitstatus = RESET;
|
696 | }
|
697 | return bitstatus;
|
698 | }
|
699 |
|
700 |
|
701 | /**
|
702 | * @brief Initiate a Pause Control Frame (Full-duplex only).
|
703 | * @param None
|
704 | * @retval None
|
705 | */
|
706 | void ETH_InitiatePauseControlFrame(void)
|
707 | {
|
708 | /* When Set In full duplex MAC initiates pause control frame */
|
709 | ETH->MACFCR |= ETH_MACFCR_FCBBPA;
|
710 | }
|
711 |
|
712 |
|
713 | /**
|
714 | * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only).
|
715 | * @param NewState: new state of the MAC BackPressure operation activation.
|
716 | * This parameter can be: ENABLE or DISABLE.
|
717 | * @retval None
|
718 | */
|
719 | void ETH_BackPressureActivationCmd(FunctionalState NewState)
|
720 | {
|
721 | /* Check the parameters */
|
722 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
723 |
|
724 | if (NewState != DISABLE)
|
725 | {
|
726 | /* Activate the MAC BackPressure operation */
|
727 | /* In Half duplex: during backpressure, when the MAC receives a new frame,
|
728 | the transmitter starts sending a JAM pattern resulting in a collision */
|
729 | ETH->MACFCR |= ETH_MACFCR_FCBBPA;
|
730 | }
|
731 | else
|
732 | {
|
733 | /* Desactivate the MAC BackPressure operation */
|
734 | ETH->MACFCR &= ~ETH_MACFCR_FCBBPA;
|
735 | }
|
736 | }
|
737 |
|
738 |
|
739 | /**
|
740 | * @brief Checks whether the specified ETHERNET MAC flag is set or not.
|
741 | * @param ETH_MAC_FLAG: specifies the flag to check.
|
742 | * This parameter can be one of the following values:
|
743 | * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
|
744 | * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
|
745 | * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
|
746 | * @arg ETH_MAC_FLAG_MMC : MMC flag
|
747 | * @arg ETH_MAC_FLAG_PMT : PMT flag
|
748 | * @retval The new state of ETHERNET MAC flag (SET or RESET).
|
749 | */
|
750 | FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)
|
751 | {
|
752 | FlagStatus bitstatus = RESET;
|
753 | /* Check the parameters */
|
754 | assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG));
|
755 | if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET)
|
756 | {
|
757 | bitstatus = SET;
|
758 | }
|
759 | else
|
760 | {
|
761 | bitstatus = RESET;
|
762 | }
|
763 | return bitstatus;
|
764 | }
|
765 |
|
766 |
|
767 | /**
|
768 | * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not.
|
769 | * @param ETH_MAC_IT: specifies the interrupt source to check.
|
770 | * This parameter can be one of the following values:
|
771 | * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
|
772 | * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt
|
773 | * @arg ETH_MAC_IT_MMCR : MMC receive interrupt
|
774 | * @arg ETH_MAC_IT_MMC : MMC interrupt
|
775 | * @arg ETH_MAC_IT_PMT : PMT interrupt
|
776 | * @retval The new state of ETHERNET MAC interrupt (SET or RESET).
|
777 | */
|
778 | ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)
|
779 | {
|
780 | ITStatus bitstatus = RESET;
|
781 | /* Check the parameters */
|
782 | assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT));
|
783 | if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET)
|
784 | {
|
785 | bitstatus = SET;
|
786 | }
|
787 | else
|
788 | {
|
789 | bitstatus = RESET;
|
790 | }
|
791 | return bitstatus;
|
792 | }
|
793 |
|
794 |
|
795 | /**
|
796 | * @brief Enables or disables the specified ETHERNET MAC interrupts.
|
797 | * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be
|
798 | * enabled or disabled.
|
799 | * This parameter can be any combination of the following values:
|
800 | * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
|
801 | * @arg ETH_MAC_IT_PMT : PMT interrupt
|
802 | * @param NewState: new state of the specified ETHERNET MAC interrupts.
|
803 | * This parameter can be: ENABLE or DISABLE.
|
804 | * @retval None
|
805 | */
|
806 | void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)
|
807 | {
|
808 | /* Check the parameters */
|
809 | assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));
|
810 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
811 |
|
812 | if (NewState != DISABLE)
|
813 | {
|
814 | /* Enable the selected ETHERNET MAC interrupts */
|
815 | ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT);
|
816 | }
|
817 | else
|
818 | {
|
819 | /* Disable the selected ETHERNET MAC interrupts */
|
820 | ETH->MACIMR |= ETH_MAC_IT;
|
821 | }
|
822 | }
|
823 |
|
824 |
|
825 | /**
|
826 | * @brief Configures the selected MAC address.
|
827 | * @param MacAddr: The MAC address to configure.
|
828 | * This parameter can be one of the following values:
|
829 | * @arg ETH_MAC_Address0 : MAC Address0
|
830 | * @arg ETH_MAC_Address1 : MAC Address1
|
831 | * @arg ETH_MAC_Address2 : MAC Address2
|
832 | * @arg ETH_MAC_Address3 : MAC Address3
|
833 | * @param Addr: Pointer on MAC address buffer data (6 bytes).
|
834 | * @retval None
|
835 | */
|
836 | void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)
|
837 | {
|
838 | uint32_t tmpreg;
|
839 | /* Check the parameters */
|
840 | assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
|
841 |
|
842 | /* Calculate the selected MAC address high register */
|
843 | tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
|
844 | /* Load the selected MAC address high register */
|
845 | (*(volatile uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg;
|
846 | /* Calculate the selected MAC address low register */
|
847 | tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
|
848 |
|
849 | /* Load the selected MAC address low register */
|
850 | (*(volatile uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg;
|
851 | }
|
852 |
|
853 |
|
854 | /**
|
855 | * @brief Get the selected MAC address.
|
856 | * @param MacAddr: The MAC address to return.
|
857 | * This parameter can be one of the following values:
|
858 | * @arg ETH_MAC_Address0 : MAC Address0
|
859 | * @arg ETH_MAC_Address1 : MAC Address1
|
860 | * @arg ETH_MAC_Address2 : MAC Address2
|
861 | * @arg ETH_MAC_Address3 : MAC Address3
|
862 | * @param Addr: Pointer on MAC address buffer data (6 bytes).
|
863 | * @retval None
|
864 | */
|
865 | void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr)
|
866 | {
|
867 | uint32_t tmpreg;
|
868 | /* Check the parameters */
|
869 | assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
|
870 |
|
871 | /* Get the selected MAC address high register */
|
872 | tmpreg =(*(volatile uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr));
|
873 |
|
874 | /* Calculate the selected MAC address buffer */
|
875 | Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF);
|
876 | Addr[4] = (tmpreg & (uint8_t)0xFF);
|
877 | /* Load the selected MAC address low register */
|
878 | tmpreg =(*(volatile uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr));
|
879 | /* Calculate the selected MAC address buffer */
|
880 | Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF);
|
881 | Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF);
|
882 | Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF);
|
883 | Addr[0] = (tmpreg & (uint8_t)0xFF);
|
884 | }
|
885 |
|
886 |
|
887 | /**
|
888 | * @brief Enables or disables the Address filter module uses the specified
|
889 | * ETHERNET MAC address for perfect filtering
|
890 | * @param MacAddr: specifies the ETHERNET MAC address to be used for perfect filtering.
|
891 | * This parameter can be one of the following values:
|
892 | * @arg ETH_MAC_Address1 : MAC Address1
|
893 | * @arg ETH_MAC_Address2 : MAC Address2
|
894 | * @arg ETH_MAC_Address3 : MAC Address3
|
895 | * @param NewState: new state of the specified ETHERNET MAC address use.
|
896 | * This parameter can be: ENABLE or DISABLE.
|
897 | * @retval None
|
898 | */
|
899 | void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState)
|
900 | {
|
901 | /* Check the parameters */
|
902 | assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
|
903 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
904 |
|
905 | if (NewState != DISABLE)
|
906 | {
|
907 | /* Enable the selected ETHERNET MAC address for perfect filtering */
|
908 | (*(volatile uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE;
|
909 | }
|
910 | else
|
911 | {
|
912 | /* Disable the selected ETHERNET MAC address for perfect filtering */
|
913 | (*(volatile uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE);
|
914 | }
|
915 | }
|
916 |
|
917 |
|
918 | /**
|
919 | * @brief Set the filter type for the specified ETHERNET MAC address
|
920 | * @param MacAddr: specifies the ETHERNET MAC address
|
921 | * This parameter can be one of the following values:
|
922 | * @arg ETH_MAC_Address1 : MAC Address1
|
923 | * @arg ETH_MAC_Address2 : MAC Address2
|
924 | * @arg ETH_MAC_Address3 : MAC Address3
|
925 | * @param Filter: specifies the used frame received field for comparison
|
926 | * This parameter can be one of the following values:
|
927 | * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare with the
|
928 | * SA fields of the received frame.
|
929 | * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare with the
|
930 | * DA fields of the received frame.
|
931 | * @retval None
|
932 | */
|
933 | void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter)
|
934 | {
|
935 | /* Check the parameters */
|
936 | assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
|
937 | assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));
|
938 |
|
939 | if (Filter != ETH_MAC_AddressFilter_DA)
|
940 | {
|
941 | /* The selected ETHERNET MAC address is used to compare with the SA fields of the
|
942 | received frame. */
|
943 | (*(volatile uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA;
|
944 | }
|
945 | else
|
946 | {
|
947 | /* The selected ETHERNET MAC address is used to compare with the DA fields of the
|
948 | received frame. */
|
949 | (*(volatile uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA);
|
950 | }
|
951 | }
|
952 |
|
953 |
|
954 | /**
|
955 | * @brief Set the filter type for the specified ETHERNET MAC address
|
956 | * @param MacAddr: specifies the ETHERNET MAC address
|
957 | * This parameter can be one of the following values:
|
958 | * @arg ETH_MAC_Address1 : MAC Address1
|
959 | * @arg ETH_MAC_Address2 : MAC Address2
|
960 | * @arg ETH_MAC_Address3 : MAC Address3
|
961 | * @param MaskByte: specifies the used address bytes for comparison
|
962 | * This parameter can be any combination of the following values:
|
963 | * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].
|
964 | * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].
|
965 | * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].
|
966 | * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].
|
967 | * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].
|
968 | * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].
|
969 | * @retval None
|
970 | */
|
971 | void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte)
|
972 | {
|
973 | /* Check the parameters */
|
974 | assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
|
975 | assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));
|
976 |
|
977 | /* Clear MBC bits in the selected MAC address high register */
|
978 | (*(volatile uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC);
|
979 | /* Set the selected Filter mask bytes */
|
980 | (*(volatile uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte;
|
981 | }
|
982 |
|
983 |
|
984 | /******************************************************************************/
|
985 | /* DMA Descriptors functions */
|
986 | /******************************************************************************/
|
987 |
|
988 | /**
|
989 | * @brief This function should be called to get the received frame (to be used
|
990 | * with polling method only).
|
991 | * @param none
|
992 | * @retval Structure of type FrameTypeDef
|
993 | */
|
994 | FrameTypeDef ETH_Get_Received_Frame(void)
|
995 | {
|
996 | uint32_t framelength = 0;
|
997 | FrameTypeDef frame = {0,0,0};
|
998 |
|
999 | /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
|
1000 | framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
|
1001 | frame.length = framelength;
|
1002 |
|
1003 | /* Get the address of the buffer start address */
|
1004 | /* Check if more than one segment in the frame */
|
1005 | if (DMA_RX_FRAME_infos->Seg_Count >1)
|
1006 | {
|
1007 | frame.buffer =(DMA_RX_FRAME_infos->FS_Rx_Desc)->Buffer1Addr;
|
1008 | }
|
1009 | else
|
1010 | {
|
1011 | frame.buffer = DMARxDescToGet->Buffer1Addr;
|
1012 | }
|
1013 |
|
1014 | frame.descriptor = DMARxDescToGet;
|
1015 |
|
1016 | /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */
|
1017 | /* Chained Mode */
|
1018 | /* Selects the next DMA Rx descriptor list for next buffer to read */
|
1019 | DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
1020 |
|
1021 | /* Return Frame */
|
1022 | return (frame);
|
1023 | }
|
1024 |
|
1025 |
|
1026 | /**
|
1027 | * @brief This function should be called when a frame is received using DMA
|
1028 | * Receive interrupt, it allows scanning of Rx descriptors to get the
|
1029 | * the receive frame (should be used with interrupt mode only)
|
1030 | * @param None
|
1031 | * @retval Structure of type FrameTypeDef
|
1032 | */
|
1033 | FrameTypeDef ETH_Get_Received_Frame_interrupt(void)
|
1034 | {
|
1035 | FrameTypeDef frame={0,0,0};
|
1036 | volatile uint32_t descriptor_scan_counter = 0;
|
1037 |
|
1038 | /* scan descriptors owned by CPU */
|
1039 | while (((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET)&&
|
1040 | (descriptor_scan_counter<ETH_RXBUFNB))
|
1041 | {
|
1042 |
|
1043 | /* Just by security */
|
1044 | descriptor_scan_counter++;
|
1045 |
|
1046 | /* check if first segment in frame */
|
1047 | if(((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)&&
|
1048 | ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET))
|
1049 | {
|
1050 | DMA_RX_FRAME_infos->FS_Rx_Desc = DMARxDescToGet;
|
1051 | DMA_RX_FRAME_infos->Seg_Count = 1;
|
1052 | DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
1053 | }
|
1054 |
|
1055 | /* check if intermediate segment */
|
1056 | else if (((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET)&&
|
1057 | ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) == (uint32_t)RESET))
|
1058 | {
|
1059 | (DMA_RX_FRAME_infos->Seg_Count) ++;
|
1060 | DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
1061 | }
|
1062 |
|
1063 | /* should be last segment */
|
1064 | else
|
1065 | {
|
1066 | /* last segment */
|
1067 | DMA_RX_FRAME_infos->LS_Rx_Desc = DMARxDescToGet;
|
1068 |
|
1069 | (DMA_RX_FRAME_infos->Seg_Count)++;
|
1070 |
|
1071 | /* first segment is last segment */
|
1072 | if ((DMA_RX_FRAME_infos->Seg_Count)==1)
|
1073 | DMA_RX_FRAME_infos->FS_Rx_Desc = DMARxDescToGet;
|
1074 |
|
1075 | /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
|
1076 | frame.length = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
|
1077 |
|
1078 |
|
1079 | /* Get the address of the buffer start address */
|
1080 | /* Check if more than one segment in the frame */
|
1081 | if (DMA_RX_FRAME_infos->Seg_Count >1)
|
1082 | {
|
1083 | frame.buffer =(DMA_RX_FRAME_infos->FS_Rx_Desc)->Buffer1Addr;
|
1084 | }
|
1085 | else
|
1086 | {
|
1087 | frame.buffer = DMARxDescToGet->Buffer1Addr;
|
1088 | }
|
1089 |
|
1090 | frame.descriptor = DMARxDescToGet;
|
1091 |
|
1092 | /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */
|
1093 | DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
1094 |
|
1095 | /* Return Frame */
|
1096 | return (frame);
|
1097 | }
|
1098 | }
|
1099 | return (frame);
|
1100 | }
|
1101 |
|
1102 |
|
1103 | /**
|
1104 | * @brief Prepares DMA Tx descriptors to transmit an ethernet frame
|
1105 | * @param FrameLength : length of the frame to send
|
1106 | * @retval error status
|
1107 | */
|
1108 | uint32_t ETH_Prepare_Transmit_Descriptors(u16 FrameLength)
|
1109 | {
|
1110 | uint32_t buf_count =0, size=0,i=0;
|
1111 | volatile ETH_DMADESCTypeDef *DMATxNextDesc;
|
1112 |
|
1113 | /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
1114 | if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
|
1115 | {
|
1116 | /* Return ERROR: OWN bit set */
|
1117 | return ETH_ERROR;
|
1118 | }
|
1119 |
|
1120 | DMATxNextDesc = DMATxDescToSet;
|
1121 |
|
1122 | if (FrameLength > ETH_TX_BUF_SIZE)
|
1123 | {
|
1124 | buf_count = FrameLength/ETH_TX_BUF_SIZE;
|
1125 | if (FrameLength%ETH_TX_BUF_SIZE) buf_count++;
|
1126 | }
|
1127 | else buf_count =1;
|
1128 |
|
1129 | if (buf_count ==1)
|
1130 | {
|
1131 | /*set LAST and FIRST segment */
|
1132 | DMATxDescToSet->Status |=ETH_DMATxDesc_FS|ETH_DMATxDesc_LS;
|
1133 | /* Set frame size */
|
1134 | DMATxDescToSet->ControlBufferSize = (FrameLength& ETH_DMATxDesc_TBS1);
|
1135 | /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
1136 | DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
|
1137 | DMATxDescToSet= (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr);
|
1138 | }
|
1139 | else
|
1140 | {
|
1141 | for (i=0; i< buf_count; i++)
|
1142 | {
|
1143 | if (i==0)
|
1144 | {
|
1145 | /* Setting the first segment bit */
|
1146 | DMATxDescToSet->Status |= ETH_DMATxDesc_FS;
|
1147 | }
|
1148 |
|
1149 | /* Program size */
|
1150 | DMATxNextDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATxDesc_TBS1);
|
1151 |
|
1152 | if (i== (buf_count-1))
|
1153 | {
|
1154 | /* Setting the last segment bit */
|
1155 | DMATxNextDesc->Status |= ETH_DMATxDesc_LS;
|
1156 | size = FrameLength - (buf_count-1)*ETH_TX_BUF_SIZE;
|
1157 | DMATxNextDesc->ControlBufferSize = (size & ETH_DMATxDesc_TBS1);
|
1158 | }
|
1159 |
|
1160 | /*give back descriptor to DMA */
|
1161 | DMATxNextDesc->Status |= ETH_DMATxDesc_OWN;
|
1162 |
|
1163 | DMATxNextDesc = (ETH_DMADESCTypeDef *)(DMATxNextDesc->Buffer2NextDescAddr);
|
1164 | /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
1165 | }
|
1166 | DMATxDescToSet = DMATxNextDesc ;
|
1167 | }
|
1168 |
|
1169 | /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
|
1170 | if ((ETH->DMASR & ETH_DMASR_TBUS) != (u32)RESET)
|
1171 | {
|
1172 | /* Clear TBUS ETHERNET DMA flag */
|
1173 | ETH->DMASR = ETH_DMASR_TBUS;
|
1174 | /* Resume DMA transmission*/
|
1175 | ETH->DMATPDR = 0;
|
1176 | }
|
1177 |
|
1178 | /* Return SUCCESS */
|
1179 | return ETH_SUCCESS;
|
1180 | }
|
1181 |
|
1182 |
|
1183 | /**
|
1184 | * @brief Initializes the DMA Rx descriptors in chain mode.
|
1185 | * @param DMARxDescTab: Pointer on the first Rx desc list
|
1186 | * @param RxBuff: Pointer on the first RxBuffer list
|
1187 | * @param RxBuffCount: Number of the used Rx desc in the list
|
1188 | * @retval None
|
1189 | */
|
1190 | void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
|
1191 | {
|
1192 | uint32_t i = 0;
|
1193 | ETH_DMADESCTypeDef *DMARxDesc;
|
1194 |
|
1195 | /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
|
1196 | DMARxDescToGet = DMARxDescTab;
|
1197 | /* Fill each DMARxDesc descriptor with the right values */
|
1198 | for(i=0; i < RxBuffCount; i++)
|
1199 | {
|
1200 | /* Get the pointer on the ith member of the Rx Desc list */
|
1201 | DMARxDesc = DMARxDescTab+i;
|
1202 | /* Set Own bit of the Rx descriptor Status */
|
1203 | DMARxDesc->Status = ETH_DMARxDesc_OWN;
|
1204 |
|
1205 | /* Set Buffer1 size and Second Address Chained bit */
|
1206 | DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_RX_BUF_SIZE;
|
1207 | /* Set Buffer1 address pointer */
|
1208 | DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
|
1209 |
|
1210 | /* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
1211 | if(i < (RxBuffCount-1))
|
1212 | {
|
1213 | /* Set next descriptor address register with next descriptor base address */
|
1214 | DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
|
1215 | }
|
1216 | else
|
1217 | {
|
1218 | /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
|
1219 | DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
|
1220 | }
|
1221 | }
|
1222 |
|
1223 | /* Set Receive Descriptor List Address Register */
|
1224 | ETH->DMARDLAR = (uint32_t) DMARxDescTab;
|
1225 |
|
1226 |
|
1227 | DMA_RX_FRAME_infos = &RX_Frame_Descriptor;
|
1228 |
|
1229 | }
|
1230 |
|
1231 | /**
|
1232 | * @brief This function polls for a frame reception
|
1233 | * @param None
|
1234 | * @retval Returns 1 when a frame is received, 0 if none.
|
1235 | */
|
1236 | uint32_t ETH_CheckFrameReceived(void)
|
1237 | {
|
1238 | /* check if last segment */
|
1239 | if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
1240 | ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET))
|
1241 | {
|
1242 | DMA_RX_FRAME_infos->LS_Rx_Desc = DMARxDescToGet;
|
1243 | DMA_RX_FRAME_infos->Seg_Count++;
|
1244 | return 1;
|
1245 | }
|
1246 |
|
1247 | /* check if first segment */
|
1248 | else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
1249 | ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)&&
|
1250 | ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET))
|
1251 | {
|
1252 | DMA_RX_FRAME_infos->FS_Rx_Desc = DMARxDescToGet;
|
1253 | DMA_RX_FRAME_infos->LS_Rx_Desc = NULL;
|
1254 | DMA_RX_FRAME_infos->Seg_Count = 1;
|
1255 | DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
1256 | }
|
1257 |
|
1258 | /* check if intermediate segment */
|
1259 | else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
1260 | ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) == (uint32_t)RESET)&&
|
1261 | ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET))
|
1262 | {
|
1263 | (DMA_RX_FRAME_infos->Seg_Count) ++;
|
1264 | DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
1265 | }
|
1266 | return 0;
|
1267 | }
|
1268 |
|
1269 |
|
1270 |
|
1271 | /**
|
1272 | * @brief Initializes the DMA Tx descriptors in chain mode.
|
1273 | * @param DMATxDescTab: Pointer on the first Tx desc list
|
1274 | * @param TxBuff: Pointer on the first TxBuffer list
|
1275 | * @param TxBuffCount: Number of the used Tx desc in the list
|
1276 | * @retval None
|
1277 | */
|
1278 | void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
|
1279 | {
|
1280 | uint32_t i = 0;
|
1281 | ETH_DMADESCTypeDef *DMATxDesc;
|
1282 |
|
1283 | /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
|
1284 | DMATxDescToSet = DMATxDescTab;
|
1285 | /* Fill each DMATxDesc descriptor with the right values */
|
1286 | for(i=0; i < TxBuffCount; i++)
|
1287 | {
|
1288 | /* Get the pointer on the ith member of the Tx Desc list */
|
1289 | DMATxDesc = DMATxDescTab + i;
|
1290 | /* Set Second Address Chained bit */
|
1291 | DMATxDesc->Status = ETH_DMATxDesc_TCH;
|
1292 |
|
1293 | /* Set Buffer1 address pointer */
|
1294 | DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
|
1295 |
|
1296 | /* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
1297 | if(i < (TxBuffCount-1))
|
1298 | {
|
1299 | /* Set next descriptor address register with next descriptor base address */
|
1300 | DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
|
1301 | }
|
1302 | else
|
1303 | {
|
1304 | /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
|
1305 | DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
|
1306 | }
|
1307 | }
|
1308 |
|
1309 | /* Set Transmit Desciptor List Address Register */
|
1310 | ETH->DMATDLAR = (uint32_t) DMATxDescTab;
|
1311 | }
|
1312 |
|
1313 |
|
1314 |
|
1315 |
|
1316 | /**
|
1317 | * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
|
1318 | * @param DMATxDesc: pointer on a DMA Tx descriptor
|
1319 | * @param ETH_DMATxDescFlag: specifies the flag to check.
|
1320 | * This parameter can be one of the following values:
|
1321 | * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine
|
1322 | * @arg ETH_DMATxDesc_IC : Interrupt on completion
|
1323 | * @arg ETH_DMATxDesc_LS : Last Segment
|
1324 | * @arg ETH_DMATxDesc_FS : First Segment
|
1325 | * @arg ETH_DMATxDesc_DC : Disable CRC
|
1326 | * @arg ETH_DMATxDesc_DP : Disable Pad
|
1327 | * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable
|
1328 | * @arg ETH_DMATxDesc_CIC : Checksum insertion control
|
1329 | * @arg ETH_DMATxDesc_TER : Transmit End of Ring
|
1330 | * @arg ETH_DMATxDesc_TCH : Second Address Chained
|
1331 | * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status
|
1332 | * @arg ETH_DMATxDesc_IHE : IP Header Error
|
1333 | * @arg ETH_DMATxDesc_ES : Error summary
|
1334 | * @arg ETH_DMATxDesc_JT : Jabber Timeout
|
1335 | * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush
|
1336 | * @arg ETH_DMATxDesc_PCE : Payload Checksum Error
|
1337 | * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during transmission
|
1338 | * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the transceiver
|
1339 | * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision
|
1340 | * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions
|
1341 | * @arg ETH_DMATxDesc_VF : VLAN Frame
|
1342 | * @arg ETH_DMATxDesc_CC : Collision Count
|
1343 | * @arg ETH_DMATxDesc_ED : Excessive Deferral
|
1344 | * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory
|
1345 | * @arg ETH_DMATxDesc_DB : Deferred Bit
|
1346 | * @retval The new state of ETH_DMATxDescFlag (SET or RESET).
|
1347 | */
|
1348 | FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)
|
1349 | {
|
1350 | FlagStatus bitstatus = RESET;
|
1351 | /* Check the parameters */
|
1352 | assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));
|
1353 |
|
1354 | if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET)
|
1355 | {
|
1356 | bitstatus = SET;
|
1357 | }
|
1358 | else
|
1359 | {
|
1360 | bitstatus = RESET;
|
1361 | }
|
1362 | return bitstatus;
|
1363 | }
|
1364 |
|
1365 | /**
|
1366 | * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
|
1367 | * @param DMATxDesc: pointer on a DMA Tx descriptor
|
1368 | * @retval The Transmit descriptor collision counter value.
|
1369 | */
|
1370 | uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
|
1371 | {
|
1372 | /* Return the Receive descriptor frame length */
|
1373 | return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT);
|
1374 | }
|
1375 |
|
1376 | /**
|
1377 | * @brief Set the specified DMA Tx Desc Own bit.
|
1378 | * @param DMATxDesc: Pointer on a Tx desc
|
1379 | * @retval None
|
1380 | */
|
1381 | void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
|
1382 | {
|
1383 | /* Set the DMA Tx Desc Own bit */
|
1384 | DMATxDesc->Status |= ETH_DMATxDesc_OWN;
|
1385 | }
|
1386 |
|
1387 | /**
|
1388 | * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt.
|
1389 | * @param DMATxDesc: Pointer on a Tx desc
|
1390 | * @param NewState: new state of the DMA Tx Desc transmit interrupt.
|
1391 | * This parameter can be: ENABLE or DISABLE.
|
1392 | * @retval None
|
1393 | */
|
1394 | void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
|
1395 | {
|
1396 | /* Check the parameters */
|
1397 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1398 |
|
1399 | if (NewState != DISABLE)
|
1400 | {
|
1401 | /* Enable the DMA Tx Desc Transmit interrupt */
|
1402 | DMATxDesc->Status |= ETH_DMATxDesc_IC;
|
1403 | }
|
1404 | else
|
1405 | {
|
1406 | /* Disable the DMA Tx Desc Transmit interrupt */
|
1407 | DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC);
|
1408 | }
|
1409 | }
|
1410 |
|
1411 | /**
|
1412 | * @brief configure Tx descriptor as last or first segment
|
1413 | * @param DMATxDesc: Pointer on a Tx desc
|
1414 | * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment.
|
1415 | * This parameter can be one of the following values:
|
1416 | * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment
|
1417 | * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment
|
1418 | * @retval None
|
1419 | */
|
1420 | void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment)
|
1421 | {
|
1422 | /* Check the parameters */
|
1423 | assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));
|
1424 |
|
1425 | /* Selects the DMA Tx Desc Frame segment */
|
1426 | DMATxDesc->Status |= DMATxDesc_FrameSegment;
|
1427 | }
|
1428 |
|
1429 | /**
|
1430 | * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
|
1431 | * @param DMATxDesc: pointer on a DMA Tx descriptor
|
1432 | * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion.
|
1433 | * This parameter can be one of the following values:
|
1434 | * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass
|
1435 | * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum
|
1436 | * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
|
1437 | * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header
|
1438 | * @retval None
|
1439 | */
|
1440 | void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)
|
1441 | {
|
1442 | /* Check the parameters */
|
1443 | assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
|
1444 |
|
1445 | /* Set the selected DMA Tx desc checksum insertion control */
|
1446 | DMATxDesc->Status |= DMATxDesc_Checksum;
|
1447 | }
|
1448 |
|
1449 | /**
|
1450 | * @brief Enables or disables the DMA Tx Desc CRC.
|
1451 | * @param DMATxDesc: pointer on a DMA Tx descriptor
|
1452 | * @param NewState: new state of the specified DMA Tx Desc CRC.
|
1453 | * This parameter can be: ENABLE or DISABLE.
|
1454 | * @retval None
|
1455 | */
|
1456 | void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
|
1457 | {
|
1458 | /* Check the parameters */
|
1459 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1460 |
|
1461 | if (NewState != DISABLE)
|
1462 | {
|
1463 | /* Enable the selected DMA Tx Desc CRC */
|
1464 | DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC);
|
1465 | }
|
1466 | else
|
1467 | {
|
1468 | /* Disable the selected DMA Tx Desc CRC */
|
1469 | DMATxDesc->Status |= ETH_DMATxDesc_DC;
|
1470 | }
|
1471 | }
|
1472 |
|
1473 |
|
1474 | /**
|
1475 | * @brief Enables or disables the DMA Tx Desc second address chained.
|
1476 | * @param DMATxDesc: pointer on a DMA Tx descriptor
|
1477 | * @param NewState: new state of the specified DMA Tx Desc second address chained.
|
1478 | * This parameter can be: ENABLE or DISABLE.
|
1479 | * @retval None
|
1480 | */
|
1481 | void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
|
1482 | {
|
1483 | /* Check the parameters */
|
1484 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1485 |
|
1486 | if (NewState != DISABLE)
|
1487 | {
|
1488 | /* Enable the selected DMA Tx Desc second address chained */
|
1489 | DMATxDesc->Status |= ETH_DMATxDesc_TCH;
|
1490 | }
|
1491 | else
|
1492 | {
|
1493 | /* Disable the selected DMA Tx Desc second address chained */
|
1494 | DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH);
|
1495 | }
|
1496 | }
|
1497 |
|
1498 | /**
|
1499 | * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
|
1500 | * @param DMATxDesc: pointer on a DMA Tx descriptor
|
1501 | * @param NewState: new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes.
|
1502 | * This parameter can be: ENABLE or DISABLE.
|
1503 | * @retval None
|
1504 | */
|
1505 | void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
|
1506 | {
|
1507 | /* Check the parameters */
|
1508 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1509 |
|
1510 | if (NewState != DISABLE)
|
1511 | {
|
1512 | /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */
|
1513 | DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP);
|
1514 | }
|
1515 | else
|
1516 | {
|
1517 | /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/
|
1518 | DMATxDesc->Status |= ETH_DMATxDesc_DP;
|
1519 | }
|
1520 | }
|
1521 |
|
1522 |
|
1523 | /**
|
1524 | * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
|
1525 | * @param DMATxDesc: Pointer on a Tx desc
|
1526 | * @param BufferSize1: specifies the Tx desc buffer1 size.
|
1527 | * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).
|
1528 | * @retval None
|
1529 | */
|
1530 | void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2)
|
1531 | {
|
1532 | /* Check the parameters */
|
1533 | assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));
|
1534 | assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));
|
1535 |
|
1536 | /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */
|
1537 | DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT));
|
1538 | }
|
1539 |
|
1540 |
|
1541 | /**
|
1542 | * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not.
|
1543 | * @param DMARxDesc: pointer on a DMA Rx descriptor
|
1544 | * @param ETH_DMARxDescFlag: specifies the flag to check.
|
1545 | * This parameter can be one of the following values:
|
1546 | * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine
|
1547 | * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame
|
1548 | * @arg ETH_DMARxDesc_ES: Error summary
|
1549 | * @arg ETH_DMARxDesc_DE: Descriptor error: no more descriptors for receive frame
|
1550 | * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame
|
1551 | * @arg ETH_DMARxDesc_LE: Frame size not matching with length field
|
1552 | * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow
|
1553 | * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame
|
1554 | * @arg ETH_DMARxDesc_FS: First descriptor of the frame
|
1555 | * @arg ETH_DMARxDesc_LS: Last descriptor of the frame
|
1556 | * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error
|
1557 | * @arg ETH_DMARxDesc_LC: Late collision occurred during reception
|
1558 | * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3
|
1559 | * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception
|
1560 | * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface
|
1561 | * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits
|
1562 | * @arg ETH_DMARxDesc_CE: CRC error
|
1563 | * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
|
1564 | * @retval The new state of ETH_DMARxDescFlag (SET or RESET).
|
1565 | */
|
1566 | FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)
|
1567 | {
|
1568 | FlagStatus bitstatus = RESET;
|
1569 | /* Check the parameters */
|
1570 | assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));
|
1571 | if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET)
|
1572 | {
|
1573 | bitstatus = SET;
|
1574 | }
|
1575 | else
|
1576 | {
|
1577 | bitstatus = RESET;
|
1578 | }
|
1579 | return bitstatus;
|
1580 | }
|
1581 |
|
1582 | #ifdef USE_ENHANCED_DMA_DESCRIPTORS
|
1583 | /**
|
1584 | * @brief Checks whether the specified ETHERNET PTP Rx Desc extended flag is set or not.
|
1585 | * @param DMAPTPRxDesc: pointer on a DMA PTP Rx descriptor
|
1586 | * @param ETH_DMAPTPRxDescFlag: specifies the extended flag to check.
|
1587 | * This parameter can be one of the following values:
|
1588 | * @arg ETH_DMAPTPRxDesc_PTPV: PTP version
|
1589 | * @arg ETH_DMAPTPRxDesc_PTPFT: PTP frame type
|
1590 | * @arg ETH_DMAPTPRxDesc_PTPMT: PTP message type
|
1591 | * @arg ETH_DMAPTPRxDesc_IPV6PR: IPv6 packet received
|
1592 | * @arg ETH_DMAPTPRxDesc_IPV4PR: IPv4 packet received
|
1593 | * @arg ETH_DMAPTPRxDesc_IPCB: IP checksum bypassed
|
1594 | * @arg ETH_DMAPTPRxDesc_IPPE: IP payload error
|
1595 | * @arg ETH_DMAPTPRxDesc_IPHE: IP header error
|
1596 | * @arg ETH_DMAPTPRxDesc_IPPT: IP payload type
|
1597 | * @retval The new state of ETH_DMAPTPRxDescExtendedFlag (SET or RESET).
|
1598 | */
|
1599 | FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag)
|
1600 | {
|
1601 | FlagStatus bitstatus = RESET;
|
1602 |
|
1603 | /* Check the parameters */
|
1604 | assert_param(IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(ETH_DMAPTPRxDescExtendedFlag));
|
1605 |
|
1606 | if ((DMAPTPRxDesc->ExtendedStatus & ETH_DMAPTPRxDescExtendedFlag) != (uint32_t)RESET)
|
1607 | {
|
1608 | bitstatus = SET;
|
1609 | }
|
1610 | else
|
1611 | {
|
1612 | bitstatus = RESET;
|
1613 | }
|
1614 | return bitstatus;
|
1615 | }
|
1616 | #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
|
1617 |
|
1618 | /**
|
1619 | * @brief Set the specified DMA Rx Desc Own bit.
|
1620 | * @param DMARxDesc: Pointer on a Rx desc
|
1621 | * @retval None
|
1622 | */
|
1623 | void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
|
1624 | {
|
1625 | /* Set the DMA Rx Desc Own bit */
|
1626 | DMARxDesc->Status |= ETH_DMARxDesc_OWN;
|
1627 | }
|
1628 |
|
1629 | /**
|
1630 | * @brief Returns the specified DMA Rx Desc frame length.
|
1631 | * @param DMARxDesc: pointer on a DMA Rx descriptor
|
1632 | * @retval The Rx descriptor received frame length.
|
1633 | */
|
1634 | uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
|
1635 | {
|
1636 | /* Return the Receive descriptor frame length */
|
1637 | return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT);
|
1638 | }
|
1639 |
|
1640 | /**
|
1641 | * @brief Enables or disables the specified DMA Rx Desc receive interrupt.
|
1642 | * @param DMARxDesc: Pointer on a Rx desc
|
1643 | * @param NewState: new state of the specified DMA Rx Desc interrupt.
|
1644 | * This parameter can be: ENABLE or DISABLE.
|
1645 | * @retval None
|
1646 | */
|
1647 | void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
|
1648 | {
|
1649 | /* Check the parameters */
|
1650 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1651 |
|
1652 | if (NewState != DISABLE)
|
1653 | {
|
1654 | /* Enable the DMA Rx Desc receive interrupt */
|
1655 | DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC);
|
1656 | }
|
1657 | else
|
1658 | {
|
1659 | /* Disable the DMA Rx Desc receive interrupt */
|
1660 | DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
|
1661 | }
|
1662 | }
|
1663 |
|
1664 |
|
1665 | /**
|
1666 | * @brief Returns the specified ETHERNET DMA Rx Desc buffer size.
|
1667 | * @param DMARxDesc: pointer on a DMA Rx descriptor
|
1668 | * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.
|
1669 | * This parameter can be any one of the following values:
|
1670 | * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
|
1671 | * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2
|
1672 | * @retval The Receive descriptor frame length.
|
1673 | */
|
1674 | uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer)
|
1675 | {
|
1676 | /* Check the parameters */
|
1677 | assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));
|
1678 |
|
1679 | if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
|
1680 | {
|
1681 | /* Return the DMA Rx Desc buffer2 size */
|
1682 | return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT);
|
1683 | }
|
1684 | else
|
1685 | {
|
1686 | /* Return the DMA Rx Desc buffer1 size */
|
1687 | return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1);
|
1688 | }
|
1689 | }
|
1690 |
|
1691 |
|
1692 | /**
|
1693 | * @brief Get the size of the received packet.
|
1694 | * @param None
|
1695 | * @retval framelength: received packet size
|
1696 | */
|
1697 | uint32_t ETH_GetRxPktSize(ETH_DMADESCTypeDef *DMARxDesc)
|
1698 | {
|
1699 | uint32_t frameLength = 0;
|
1700 | if(((DMARxDesc->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
1701 | ((DMARxDesc->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
|
1702 | ((DMARxDesc->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET))
|
1703 | {
|
1704 | /* Get the size of the packet: including 4 bytes of the CRC */
|
1705 | frameLength = ETH_GetDMARxDescFrameLength(DMARxDesc);
|
1706 | }
|
1707 |
|
1708 | /* Return Frame Length */
|
1709 | return frameLength;
|
1710 | }
|
1711 |
|
1712 | #ifdef USE_ENHANCED_DMA_DESCRIPTORS
|
1713 | /**
|
1714 | * @brief Enables or disables the Enhanced descriptor structure.
|
1715 | * @param NewState: new state of the Enhanced descriptor structure.
|
1716 | * This parameter can be: ENABLE or DISABLE.
|
1717 | * @retval None
|
1718 | */
|
1719 | void ETH_EnhancedDescriptorCmd(FunctionalState NewState)
|
1720 | {
|
1721 | /* Check the parameters */
|
1722 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1723 |
|
1724 | if (NewState != DISABLE)
|
1725 | {
|
1726 | /* Enable enhanced descriptor structure */
|
1727 | ETH->DMABMR |= ETH_DMABMR_EDE;
|
1728 | }
|
1729 | else
|
1730 | {
|
1731 | /* Disable enhanced descriptor structure */
|
1732 | ETH->DMABMR &= ~ETH_DMABMR_EDE;
|
1733 | }
|
1734 | }
|
1735 | #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
|
1736 |
|
1737 | /******************************************************************************/
|
1738 | /* DMA functions */
|
1739 | /******************************************************************************/
|
1740 | /**
|
1741 | * @brief Resets all MAC subsystem internal registers and logic.
|
1742 | * @param None
|
1743 | * @retval None
|
1744 | */
|
1745 | void ETH_SoftwareReset(void)
|
1746 | {
|
1747 | /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
|
1748 | /* After reset all the registers holds their respective reset values */
|
1749 | ETH->DMABMR |= ETH_DMABMR_SR;
|
1750 | }
|
1751 |
|
1752 | /**
|
1753 | * @brief Checks whether the ETHERNET software reset bit is set or not.
|
1754 | * @param None
|
1755 | * @retval The new state of DMA Bus Mode register SR bit (SET or RESET).
|
1756 | */
|
1757 | FlagStatus ETH_GetSoftwareResetStatus(void)
|
1758 | {
|
1759 | FlagStatus bitstatus = RESET;
|
1760 | if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
|
1761 | {
|
1762 | bitstatus = SET;
|
1763 | }
|
1764 | else
|
1765 | {
|
1766 | bitstatus = RESET;
|
1767 | }
|
1768 | return bitstatus;
|
1769 | }
|
1770 |
|
1771 | /**
|
1772 | * @brief Checks whether the specified ETHERNET DMA flag is set or not.
|
1773 | * @param ETH_DMA_FLAG: specifies the flag to check.
|
1774 | * This parameter can be one of the following values:
|
1775 | * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag
|
1776 | * @arg ETH_DMA_FLAG_PMT : PMT flag
|
1777 | * @arg ETH_DMA_FLAG_MMC : MMC flag
|
1778 | * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access
|
1779 | * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr
|
1780 | * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA
|
1781 | * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
|
1782 | * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
|
1783 | * @arg ETH_DMA_FLAG_ER : Early receive flag
|
1784 | * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
|
1785 | * @arg ETH_DMA_FLAG_ET : Early transmit flag
|
1786 | * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
|
1787 | * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
|
1788 | * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
|
1789 | * @arg ETH_DMA_FLAG_R : Receive flag
|
1790 | * @arg ETH_DMA_FLAG_TU : Underflow flag
|
1791 | * @arg ETH_DMA_FLAG_RO : Overflow flag
|
1792 | * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
|
1793 | * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
|
1794 | * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
|
1795 | * @arg ETH_DMA_FLAG_T : Transmit flag
|
1796 | * @retval The new state of ETH_DMA_FLAG (SET or RESET).
|
1797 | */
|
1798 | FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)
|
1799 | {
|
1800 | FlagStatus bitstatus = RESET;
|
1801 | /* Check the parameters */
|
1802 | assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));
|
1803 | if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET)
|
1804 | {
|
1805 | bitstatus = SET;
|
1806 | }
|
1807 | else
|
1808 | {
|
1809 | bitstatus = RESET;
|
1810 | }
|
1811 | return bitstatus;
|
1812 | }
|
1813 |
|
1814 | /**
|
1815 | * @brief Clears the ETHERNET�s DMA pending flag.
|
1816 | * @param ETH_DMA_FLAG: specifies the flag to clear.
|
1817 | * This parameter can be any combination of the following values:
|
1818 | * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
|
1819 | * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
|
1820 | * @arg ETH_DMA_FLAG_ER : Early receive flag
|
1821 | * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
|
1822 | * @arg ETH_DMA_FLAG_ETI : Early transmit flag
|
1823 | * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
|
1824 | * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
|
1825 | * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
|
1826 | * @arg ETH_DMA_FLAG_R : Receive flag
|
1827 | * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag
|
1828 | * @arg ETH_DMA_FLAG_RO : Receive Overflow flag
|
1829 | * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
|
1830 | * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
|
1831 | * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
|
1832 | * @arg ETH_DMA_FLAG_T : Transmit flag
|
1833 | * @retval None
|
1834 | */
|
1835 | void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG)
|
1836 | {
|
1837 | /* Check the parameters */
|
1838 | assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));
|
1839 |
|
1840 | /* Clear the selected ETHERNET DMA FLAG */
|
1841 | ETH->DMASR = (uint32_t) ETH_DMA_FLAG;
|
1842 | }
|
1843 |
|
1844 | /**
|
1845 | * @brief Enables or disables the specified ETHERNET DMA interrupts.
|
1846 | * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be
|
1847 | * enabled or disabled.
|
1848 | * This parameter can be any combination of the following values:
|
1849 | * @arg ETH_DMA_IT_NIS : Normal interrupt summary
|
1850 | * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
|
1851 | * @arg ETH_DMA_IT_ER : Early receive interrupt
|
1852 | * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
|
1853 | * @arg ETH_DMA_IT_ET : Early transmit interrupt
|
1854 | * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
|
1855 | * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
|
1856 | * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
|
1857 | * @arg ETH_DMA_IT_R : Receive interrupt
|
1858 | * @arg ETH_DMA_IT_TU : Underflow interrupt
|
1859 | * @arg ETH_DMA_IT_RO : Overflow interrupt
|
1860 | * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
|
1861 | * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
|
1862 | * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
|
1863 | * @arg ETH_DMA_IT_T : Transmit interrupt
|
1864 | * @param NewState: new state of the specified ETHERNET DMA interrupts.
|
1865 | * This parameter can be: ENABLE or DISABLE.
|
1866 | * @retval None
|
1867 | */
|
1868 | void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)
|
1869 | {
|
1870 | /* Check the parameters */
|
1871 | assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
|
1872 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1873 |
|
1874 | if (NewState != DISABLE)
|
1875 | {
|
1876 | /* Enable the selected ETHERNET DMA interrupts */
|
1877 | ETH->DMAIER |= ETH_DMA_IT;
|
1878 | }
|
1879 | else
|
1880 | {
|
1881 | /* Disable the selected ETHERNET DMA interrupts */
|
1882 | ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT);
|
1883 | }
|
1884 | }
|
1885 |
|
1886 | /**
|
1887 | * @brief Checks whether the specified ETHERNET DMA interrupt has occurred or not.
|
1888 | * @param ETH_DMA_IT: specifies the interrupt source to check.
|
1889 | * This parameter can be one of the following values:
|
1890 | * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt
|
1891 | * @arg ETH_DMA_IT_PMT : PMT interrupt
|
1892 | * @arg ETH_DMA_IT_MMC : MMC interrupt
|
1893 | * @arg ETH_DMA_IT_NIS : Normal interrupt summary
|
1894 | * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
|
1895 | * @arg ETH_DMA_IT_ER : Early receive interrupt
|
1896 | * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
|
1897 | * @arg ETH_DMA_IT_ET : Early transmit interrupt
|
1898 | * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
|
1899 | * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
|
1900 | * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
|
1901 | * @arg ETH_DMA_IT_R : Receive interrupt
|
1902 | * @arg ETH_DMA_IT_TU : Underflow interrupt
|
1903 | * @arg ETH_DMA_IT_RO : Overflow interrupt
|
1904 | * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
|
1905 | * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
|
1906 | * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
|
1907 | * @arg ETH_DMA_IT_T : Transmit interrupt
|
1908 | * @retval The new state of ETH_DMA_IT (SET or RESET).
|
1909 | */
|
1910 | ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)
|
1911 | {
|
1912 | ITStatus bitstatus = RESET;
|
1913 | /* Check the parameters */
|
1914 | assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));
|
1915 | if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET)
|
1916 | {
|
1917 | bitstatus = SET;
|
1918 | }
|
1919 | else
|
1920 | {
|
1921 | bitstatus = RESET;
|
1922 | }
|
1923 | return bitstatus;
|
1924 | }
|
1925 |
|
1926 | /**
|
1927 | * @brief Clears the ETHERNET�s DMA IT pending bit.
|
1928 | * @param ETH_DMA_IT: specifies the interrupt pending bit to clear.
|
1929 | * This parameter can be any combination of the following values:
|
1930 | * @arg ETH_DMA_IT_NIS : Normal interrupt summary
|
1931 | * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
|
1932 | * @arg ETH_DMA_IT_ER : Early receive interrupt
|
1933 | * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
|
1934 | * @arg ETH_DMA_IT_ETI : Early transmit interrupt
|
1935 | * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
|
1936 | * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
|
1937 | * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
|
1938 | * @arg ETH_DMA_IT_R : Receive interrupt
|
1939 | * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt
|
1940 | * @arg ETH_DMA_IT_RO : Receive Overflow interrupt
|
1941 | * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
|
1942 | * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
|
1943 | * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
|
1944 | * @arg ETH_DMA_IT_T : Transmit interrupt
|
1945 | * @retval None
|
1946 | */
|
1947 | void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT)
|
1948 | {
|
1949 | /* Check the parameters */
|
1950 | assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
|
1951 |
|
1952 | /* Clear the selected ETHERNET DMA IT */
|
1953 | ETH->DMASR = (uint32_t) ETH_DMA_IT;
|
1954 | }
|
1955 |
|
1956 | /**
|
1957 | * @brief Returns the ETHERNET DMA Transmit Process State.
|
1958 | * @param None
|
1959 | * @retval The new ETHERNET DMA Transmit Process State:
|
1960 | * This can be one of the following values:
|
1961 | * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued
|
1962 | * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor
|
1963 | * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status
|
1964 | * - ETH_DMA_TransmitProcess_Reading : Running - reading the data from host memory
|
1965 | * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Descriptor unavailable
|
1966 | * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor
|
1967 | */
|
1968 | uint32_t ETH_GetTransmitProcessState(void)
|
1969 | {
|
1970 | return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS));
|
1971 | }
|
1972 |
|
1973 | /**
|
1974 | * @brief Returns the ETHERNET DMA Receive Process State.
|
1975 | * @param None
|
1976 | * @retval The new ETHERNET DMA Receive Process State:
|
1977 | * This can be one of the following values:
|
1978 | * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued
|
1979 | * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor
|
1980 | * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet
|
1981 | * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Descriptor unavailable
|
1982 | * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor
|
1983 | * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the receive frame into host memory
|
1984 | */
|
1985 | uint32_t ETH_GetReceiveProcessState(void)
|
1986 | {
|
1987 | return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS));
|
1988 | }
|
1989 |
|
1990 | /**
|
1991 | * @brief Clears the ETHERNET transmit FIFO.
|
1992 | * @param None
|
1993 | * @retval None
|
1994 | */
|
1995 | void ETH_FlushTransmitFIFO(void)
|
1996 | {
|
1997 | /* Set the Flush Transmit FIFO bit */
|
1998 | ETH->DMAOMR |= ETH_DMAOMR_FTF;
|
1999 | }
|
2000 |
|
2001 | /**
|
2002 | * @brief Checks whether the ETHERNET flush transmit FIFO bit is cleared or not.
|
2003 | * @param None
|
2004 | * @retval The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
|
2005 | */
|
2006 | FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
|
2007 | {
|
2008 | FlagStatus bitstatus = RESET;
|
2009 | if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET)
|
2010 | {
|
2011 | bitstatus = SET;
|
2012 | }
|
2013 | else
|
2014 | {
|
2015 | bitstatus = RESET;
|
2016 | }
|
2017 | return bitstatus;
|
2018 | }
|
2019 |
|
2020 | /**
|
2021 | * @brief Enables or disables the DMA transmission.
|
2022 | * @param NewState: new state of the DMA transmission.
|
2023 | * This parameter can be: ENABLE or DISABLE.
|
2024 | * @retval None
|
2025 | */
|
2026 | void ETH_DMATransmissionCmd(FunctionalState NewState)
|
2027 | {
|
2028 | /* Check the parameters */
|
2029 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
2030 |
|
2031 | if (NewState != DISABLE)
|
2032 | {
|
2033 | /* Enable the DMA transmission */
|
2034 | ETH->DMAOMR |= ETH_DMAOMR_ST;
|
2035 | }
|
2036 | else
|
2037 | {
|
2038 | /* Disable the DMA transmission */
|
2039 | ETH->DMAOMR &= ~ETH_DMAOMR_ST;
|
2040 | }
|
2041 | }
|
2042 |
|
2043 | /**
|
2044 | * @brief Enables or disables the DMA reception.
|
2045 | * @param NewState: new state of the DMA reception.
|
2046 | * This parameter can be: ENABLE or DISABLE.
|
2047 | * @retval None
|
2048 | */
|
2049 | void ETH_DMAReceptionCmd(FunctionalState NewState)
|
2050 | {
|
2051 | /* Check the parameters */
|
2052 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
2053 |
|
2054 | if (NewState != DISABLE)
|
2055 | {
|
2056 | /* Enable the DMA reception */
|
2057 | ETH->DMAOMR |= ETH_DMAOMR_SR;
|
2058 | }
|
2059 | else
|
2060 | {
|
2061 | /* Disable the DMA reception */
|
2062 | ETH->DMAOMR &= ~ETH_DMAOMR_SR;
|
2063 | }
|
2064 | }
|
2065 |
|
2066 | /**
|
2067 | * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
|
2068 | * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check.
|
2069 | * This parameter can be one of the following values:
|
2070 | * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflows Counter
|
2071 | * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Buffer Unavailable Missed Frame Counter
|
2072 | * @retval The new state of ETHERNET DMA overflow Flag (SET or RESET).
|
2073 | */
|
2074 | FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)
|
2075 | {
|
2076 | FlagStatus bitstatus = RESET;
|
2077 | /* Check the parameters */
|
2078 | assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));
|
2079 |
|
2080 | if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET)
|
2081 | {
|
2082 | bitstatus = SET;
|
2083 | }
|
2084 | else
|
2085 | {
|
2086 | bitstatus = RESET;
|
2087 | }
|
2088 | return bitstatus;
|
2089 | }
|
2090 |
|
2091 | /**
|
2092 | * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
|
2093 | * @param None
|
2094 | * @retval The value of Rx overflow Missed Frame Counter.
|
2095 | */
|
2096 | uint32_t ETH_GetRxOverflowMissedFrameCounter(void)
|
2097 | {
|
2098 | return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT));
|
2099 | }
|
2100 |
|
2101 | /**
|
2102 | * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
|
2103 | * @param None
|
2104 | * @retval The value of Buffer unavailable Missed Frame Counter.
|
2105 | */
|
2106 | uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)
|
2107 | {
|
2108 | return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);
|
2109 | }
|
2110 |
|
2111 | /**
|
2112 | * @brief Get the ETHERNET DMA DMACHTDR register value.
|
2113 | * @param None
|
2114 | * @retval The value of the current Tx desc start address.
|
2115 | */
|
2116 | uint32_t ETH_GetCurrentTxDescStartAddress(void)
|
2117 | {
|
2118 | return ((uint32_t)(ETH->DMACHTDR));
|
2119 | }
|
2120 |
|
2121 | /**
|
2122 | * @brief Get the ETHERNET DMA DMACHRDR register value.
|
2123 | * @param None
|
2124 | * @retval The value of the current Rx desc start address.
|
2125 | */
|
2126 | uint32_t ETH_GetCurrentRxDescStartAddress(void)
|
2127 | {
|
2128 | return ((uint32_t)(ETH->DMACHRDR));
|
2129 | }
|
2130 |
|
2131 | /**
|
2132 | * @brief Get the ETHERNET DMA DMACHTBAR register value.
|
2133 | * @param None
|
2134 | * @retval The value of the current transmit descriptor data buffer address.
|
2135 | */
|
2136 | uint32_t ETH_GetCurrentTxBufferAddress(void)
|
2137 | {
|
2138 | return ((uint32_t)(ETH->DMACHTBAR));
|
2139 | }
|
2140 |
|
2141 | /**
|
2142 | * @brief Get the ETHERNET DMA DMACHRBAR register value.
|
2143 | * @param None
|
2144 | * @retval The value of the current receive descriptor data buffer address.
|
2145 | */
|
2146 | uint32_t ETH_GetCurrentRxBufferAddress(void)
|
2147 | {
|
2148 | return ((uint32_t)(ETH->DMACHRBAR));
|
2149 | }
|
2150 |
|
2151 | /**
|
2152 | * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register
|
2153 | * (the data written could be anything). This forces the DMA to resume transmission.
|
2154 | * @param None
|
2155 | * @retval None.
|
2156 | */
|
2157 | void ETH_ResumeDMATransmission(void)
|
2158 | {
|
2159 | ETH->DMATPDR = 0;
|
2160 | }
|
2161 |
|
2162 | /**
|
2163 | * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register
|
2164 | * (the data written could be anything). This forces the DMA to resume reception.
|
2165 | * @param None
|
2166 | * @retval None.
|
2167 | */
|
2168 | void ETH_ResumeDMAReception(void)
|
2169 | {
|
2170 | ETH->DMARPDR = 0;
|
2171 | }
|
2172 |
|
2173 | /**
|
2174 | * @brief Set the DMA Receive status watchdog timer register value
|
2175 | * @param Value: DMA Receive status watchdog timer register value
|
2176 | * @retval None
|
2177 | */
|
2178 | void ETH_SetReceiveWatchdogTimer(uint8_t Value)
|
2179 | {
|
2180 | /* Set the DMA Receive status watchdog timer register */
|
2181 | ETH->DMARSWTR = Value;
|
2182 | }
|
2183 |
|
2184 | /******************************************************************************/
|
2185 | /* PHY functions */
|
2186 | /******************************************************************************/
|
2187 |
|
2188 | /**
|
2189 | * @brief Read a PHY register
|
2190 | * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices.
|
2191 | * This parameter can be one of the following values: 0,..,31
|
2192 | * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
|
2193 | * This parameter can be one of the following values:
|
2194 | * @arg PHY_BCR: Transceiver Basic Control Register
|
2195 | * @arg PHY_BSR: Transceiver Basic Status Register
|
2196 | * @arg PHY_SR : Transceiver Status Register
|
2197 | * @arg More PHY register could be read depending on the used PHY
|
2198 | * @retval ETH_ERROR: in case of timeout
|
2199 | * MAC MIIDR register value: Data read from the selected PHY register (correct read )
|
2200 | */
|
2201 | uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
|
2202 | {
|
2203 | uint32_t tmpreg = 0;
|
2204 | volatile uint32_t timeout = 0;
|
2205 | /* Check the parameters */
|
2206 | assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
|
2207 | assert_param(IS_ETH_PHY_REG(PHYReg));
|
2208 |
|
2209 | /* Get the ETHERNET MACMIIAR value */
|
2210 | tmpreg = ETH->MACMIIAR;
|
2211 | /* Keep only the CSR Clock Range CR[2:0] bits value */
|
2212 | tmpreg &= ~MACMIIAR_CR_MASK;
|
2213 | /* Prepare the MII address register value */
|
2214 | tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
|
2215 | tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
|
2216 | tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
|
2217 | tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
|
2218 | /* Write the result value into the MII Address register */
|
2219 | ETH->MACMIIAR = tmpreg;
|
2220 | /* Check for the Busy flag */
|
2221 | do
|
2222 | {
|
2223 | timeout++;
|
2224 | tmpreg = ETH->MACMIIAR;
|
2225 | } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
|
2226 | /* Return ERROR in case of timeout */
|
2227 | if(timeout == PHY_READ_TO)
|
2228 | {
|
2229 | return (uint16_t)ETH_ERROR;
|
2230 | }
|
2231 |
|
2232 | /* Return data register value */
|
2233 | return (uint16_t)(ETH->MACMIIDR);
|
2234 | }
|
2235 |
|
2236 | /**
|
2237 | * @brief Write to a PHY register
|
2238 | * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices.
|
2239 | * This parameter can be one of the following values: 0,..,31
|
2240 | * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
|
2241 | * This parameter can be one of the following values:
|
2242 | * @arg PHY_BCR : Transceiver Control Register
|
2243 | * @arg More PHY register could be written depending on the used PHY
|
2244 | * @param PHYValue: the value to write
|
2245 | * @retval ETH_ERROR: in case of timeout
|
2246 | * ETH_SUCCESS: for correct write
|
2247 | */
|
2248 | uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)
|
2249 | {
|
2250 | uint32_t tmpreg = 0;
|
2251 | volatile uint32_t timeout = 0;
|
2252 | /* Check the parameters */
|
2253 | assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
|
2254 | assert_param(IS_ETH_PHY_REG(PHYReg));
|
2255 |
|
2256 | /* Get the ETHERNET MACMIIAR value */
|
2257 | tmpreg = ETH->MACMIIAR;
|
2258 | /* Keep only the CSR Clock Range CR[2:0] bits value */
|
2259 | tmpreg &= ~MACMIIAR_CR_MASK;
|
2260 | /* Prepare the MII register address value */
|
2261 | tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
|
2262 | tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
|
2263 | tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
|
2264 | tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
|
2265 | /* Give the value to the MII data register */
|
2266 | ETH->MACMIIDR = PHYValue;
|
2267 | /* Write the result value into the MII Address register */
|
2268 | ETH->MACMIIAR = tmpreg;
|
2269 | /* Check for the Busy flag */
|
2270 | do
|
2271 | {
|
2272 | timeout++;
|
2273 | tmpreg = ETH->MACMIIAR;
|
2274 | } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
|
2275 | /* Return ERROR in case of timeout */
|
2276 | if(timeout == PHY_WRITE_TO)
|
2277 | {
|
2278 | return ETH_ERROR;
|
2279 | }
|
2280 |
|
2281 | /* Return SUCCESS */
|
2282 | return ETH_SUCCESS;
|
2283 | }
|
2284 |
|
2285 | /**
|
2286 | * @brief Enables or disables the PHY loopBack mode.
|
2287 | * @Note: Don't be confused with ETH_MACLoopBackCmd function which enables internal
|
2288 | * loopback at MII level
|
2289 | * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices.
|
2290 | * @param NewState: new state of the PHY loopBack mode.
|
2291 | * This parameter can be: ENABLE or DISABLE.
|
2292 | * @retval ETH_ERROR: in case of bad PHY configuration
|
2293 | * ETH_SUCCESS: for correct PHY configuration
|
2294 | */
|
2295 | uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)
|
2296 | {
|
2297 | uint16_t tmpreg = 0;
|
2298 | /* Check the parameters */
|
2299 | assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
|
2300 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
2301 |
|
2302 | /* Get the PHY configuration to update it */
|
2303 | tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR);
|
2304 |
|
2305 | if (NewState != DISABLE)
|
2306 | {
|
2307 | /* Enable the PHY loopback mode */
|
2308 | tmpreg |= PHY_Loopback;
|
2309 | }
|
2310 | else
|
2311 | {
|
2312 | /* Disable the PHY loopback mode: normal mode */
|
2313 | tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);
|
2314 | }
|
2315 | /* Update the PHY control register with the new configuration */
|
2316 | if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)
|
2317 | {
|
2318 | return ETH_SUCCESS;
|
2319 | }
|
2320 | else
|
2321 | {
|
2322 | /* Return SUCCESS */
|
2323 | return ETH_ERROR;
|
2324 | }
|
2325 | }
|
2326 |
|
2327 | /******************************************************************************/
|
2328 | /* Power Management(PMT) functions */
|
2329 | /******************************************************************************/
|
2330 | /**
|
2331 | * @brief Reset Wakeup frame filter register pointer.
|
2332 | * @param None
|
2333 | * @retval None
|
2334 | */
|
2335 | void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
|
2336 | {
|
2337 | /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */
|
2338 | ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
|
2339 | }
|
2340 |
|
2341 | /**
|
2342 | * @brief Populates the remote wakeup frame registers.
|
2343 | * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer data (8 words).
|
2344 | * @retval None
|
2345 | */
|
2346 | void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer)
|
2347 | {
|
2348 | uint32_t i = 0;
|
2349 |
|
2350 | /* Fill Remote Wake-up Frame Filter register with Buffer data */
|
2351 | for(i =0; i<ETH_WAKEUP_REGISTER_LENGTH; i++)
|
2352 | {
|
2353 | /* Write each time to the same register */
|
2354 | ETH->MACRWUFFR = Buffer[i];
|
2355 | }
|
2356 | }
|
2357 |
|
2358 | /**
|
2359 | * @brief Enables or disables any unicast packet filtered by the MAC address
|
2360 | * recognition to be a wake-up frame.
|
2361 | * @param NewState: new state of the MAC Global Unicast Wake-Up.
|
2362 | * This parameter can be: ENABLE or DISABLE.
|
2363 | * @retval None
|
2364 | */
|
2365 | void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
|
2366 | {
|
2367 | /* Check the parameters */
|
2368 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
2369 |
|
2370 | if (NewState != DISABLE)
|
2371 | {
|
2372 | /* Enable the MAC Global Unicast Wake-Up */
|
2373 | ETH->MACPMTCSR |= ETH_MACPMTCSR_GU;
|
2374 | }
|
2375 | else
|
2376 | {
|
2377 | /* Disable the MAC Global Unicast Wake-Up */
|
2378 | ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU;
|
2379 | }
|
2380 | }
|
2381 |
|
2382 | /**
|
2383 | * @brief Checks whether the specified ETHERNET PMT flag is set or not.
|
2384 | * @param ETH_PMT_FLAG: specifies the flag to check.
|
2385 | * This parameter can be one of the following values:
|
2386 | * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
|
2387 | * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
|
2388 | * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
|
2389 | * @retval The new state of ETHERNET PMT Flag (SET or RESET).
|
2390 | */
|
2391 | FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG)
|
2392 | {
|
2393 | FlagStatus bitstatus = RESET;
|
2394 | /* Check the parameters */
|
2395 | assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));
|
2396 |
|
2397 | if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET)
|
2398 | {
|
2399 | bitstatus = SET;
|
2400 | }
|
2401 | else
|
2402 | {
|
2403 | bitstatus = RESET;
|
2404 | }
|
2405 | return bitstatus;
|
2406 | }
|
2407 |
|
2408 | /**
|
2409 | * @brief Enables or disables the MAC Wake-Up Frame Detection.
|
2410 | * @param NewState: new state of the MAC Wake-Up Frame Detection.
|
2411 | * This parameter can be: ENABLE or DISABLE.
|
2412 | * @retval None
|
2413 | */
|
2414 | void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
|
2415 | {
|
2416 | /* Check the parameters */
|
2417 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
2418 |
|
2419 | if (NewState != DISABLE)
|
2420 | {
|
2421 | /* Enable the MAC Wake-Up Frame Detection */
|
2422 | ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE;
|
2423 | }
|
2424 | else
|
2425 | {
|
2426 | /* Disable the MAC Wake-Up Frame Detection */
|
2427 | ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;
|
2428 | }
|
2429 | }
|
2430 |
|
2431 | /**
|
2432 | * @brief Enables or disables the MAC Magic Packet Detection.
|
2433 | * @param NewState: new state of the MAC Magic Packet Detection.
|
2434 | * This parameter can be: ENABLE or DISABLE.
|
2435 | * @retval None
|
2436 | */
|
2437 | void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
|
2438 | {
|
2439 | /* Check the parameters */
|
2440 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
2441 |
|
2442 | if (NewState != DISABLE)
|
2443 | {
|
2444 | /* Enable the MAC Magic Packet Detection */
|
2445 | ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE;
|
2446 | }
|
2447 | else
|
2448 | {
|
2449 | /* Disable the MAC Magic Packet Detection */
|
2450 | ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;
|
2451 | }
|
2452 | }
|
2453 |
|
2454 | /**
|
2455 | * @brief Enables or disables the MAC Power Down.
|
2456 | * @param NewState: new state of the MAC Power Down.
|
2457 | * This parameter can be: ENABLE or DISABLE.
|
2458 | * @retval None
|
2459 | */
|
2460 | void ETH_PowerDownCmd(FunctionalState NewState)
|
2461 | {
|
2462 | /* Check the parameters */
|
2463 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
2464 |
|
2465 | if (NewState != DISABLE)
|
2466 | {
|
2467 | /* Enable the MAC Power Down */
|
2468 | /* This puts the MAC in power down mode */
|
2469 | ETH->MACPMTCSR |= ETH_MACPMTCSR_PD;
|
2470 | }
|
2471 | else
|
2472 | {
|
2473 | /* Disable the MAC Power Down */
|
2474 | ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD;
|
2475 | }
|
2476 | }
|
2477 |
|
2478 | /******************************************************************************/
|
2479 | /* MMC functions */
|
2480 | /******************************************************************************/
|
2481 | /**
|
2482 | * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
|
2483 | * @param None
|
2484 | * @retval None
|
2485 | */
|
2486 | void ETH_MMCCounterFullPreset(void)
|
2487 | {
|
2488 | /* Preset and Initialize the MMC counters to almost-full value */
|
2489 | ETH->MMCCR |= ETH_MMCCR_MCFHP | ETH_MMCCR_MCP;
|
2490 | }
|
2491 |
|
2492 | /**
|
2493 | * @brief Preset and Initialize the MMC counters to almost-hal value: 0x7FFF_FFF0 (half - 16).
|
2494 | * @param None
|
2495 | * @retval None
|
2496 | */
|
2497 | void ETH_MMCCounterHalfPreset(void)
|
2498 | {
|
2499 | /* Preset the MMC counters to almost-full value */
|
2500 | ETH->MMCCR &= ~ETH_MMCCR_MCFHP;
|
2501 | /* Initialize the MMC counters to almost-half value */
|
2502 | ETH->MMCCR |= ETH_MMCCR_MCP;
|
2503 | }
|
2504 |
|
2505 | /**
|
2506 | * @brief Enables or disables the MMC Counter Freeze.
|
2507 | * @param NewState: new state of the MMC Counter Freeze.
|
2508 | * This parameter can be: ENABLE or DISABLE.
|
2509 | * @retval None
|
2510 | */
|
2511 | void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
|
2512 | {
|
2513 | /* Check the parameters */
|
2514 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
2515 |
|
2516 | if (NewState != DISABLE)
|
2517 | {
|
2518 | /* Enable the MMC Counter Freeze */
|
2519 | ETH->MMCCR |= ETH_MMCCR_MCF;
|
2520 | }
|
2521 | else
|
2522 | {
|
2523 | /* Disable the MMC Counter Freeze */
|
2524 | ETH->MMCCR &= ~ETH_MMCCR_MCF;
|
2525 | }
|
2526 | }
|
2527 |
|
2528 | /**
|
2529 | * @brief Enables or disables the MMC Reset On Read.
|
2530 | * @param NewState: new state of the MMC Reset On Read.
|
2531 | * This parameter can be: ENABLE or DISABLE.
|
2532 | * @retval None
|
2533 | */
|
2534 | void ETH_MMCResetOnReadCmd(FunctionalState NewState)
|
2535 | {
|
2536 | /* Check the parameters */
|
2537 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
2538 |
|
2539 | if (NewState != DISABLE)
|
2540 | {
|
2541 | /* Enable the MMC Counter reset on read */
|
2542 | ETH->MMCCR |= ETH_MMCCR_ROR;
|
2543 | }
|
2544 | else
|
2545 | {
|
2546 | /* Disable the MMC Counter reset on read */
|
2547 | ETH->MMCCR &= ~ETH_MMCCR_ROR;
|
2548 | }
|
2549 | }
|
2550 |
|
2551 | /**
|
2552 | * @brief Enables or disables the MMC Counter Stop Rollover.
|
2553 | * @param NewState: new state of the MMC Counter Stop Rollover.
|
2554 | * This parameter can be: ENABLE or DISABLE.
|
2555 | * @retval None
|
2556 | */
|
2557 | void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
|
2558 | {
|
2559 | /* Check the parameters */
|
2560 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
2561 |
|
2562 | if (NewState != DISABLE)
|
2563 | {
|
2564 | /* Disable the MMC Counter Stop Rollover */
|
2565 | ETH->MMCCR &= ~ETH_MMCCR_CSR;
|
2566 | }
|
2567 | else
|
2568 | {
|
2569 | /* Enable the MMC Counter Stop Rollover */
|
2570 | ETH->MMCCR |= ETH_MMCCR_CSR;
|
2571 | }
|
2572 | }
|
2573 |
|
2574 | /**
|
2575 | * @brief Resets the MMC Counters.
|
2576 | * @param None
|
2577 | * @retval None
|
2578 | */
|
2579 | void ETH_MMCCountersReset(void)
|
2580 | {
|
2581 | /* Resets the MMC Counters */
|
2582 | ETH->MMCCR |= ETH_MMCCR_CR;
|
2583 | }
|
2584 |
|
2585 | /**
|
2586 | * @brief Enables or disables the specified ETHERNET MMC interrupts.
|
2587 | * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
|
2588 | * This parameter can be any combination of Tx interrupt or
|
2589 | * any combination of Rx interrupt (but not both)of the following values:
|
2590 | * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
|
2591 | * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
|
2592 | * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
|
2593 | * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
|
2594 | * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
|
2595 | * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
|
2596 | * @param NewState: new state of the specified ETHERNET MMC interrupts.
|
2597 | * This parameter can be: ENABLE or DISABLE.
|
2598 | * @retval None
|
2599 | */
|
2600 | void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState)
|
2601 | {
|
2602 | /* Check the parameters */
|
2603 | assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));
|
2604 | assert_param(IS_FUNCTIONAL_STATE(NewState));
|
2605 |
|
2606 | if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
|
2607 | {
|
2608 | /* Remove Register mak from IT */
|
2609 | ETH_MMC_IT &= 0xEFFFFFFF;
|
2610 |
|
2611 | /* ETHERNET MMC Rx interrupts selected */
|
2612 | if (NewState != DISABLE)
|
2613 | {
|
2614 | /* Enable the selected ETHERNET MMC interrupts */
|
2615 | ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT);
|
2616 | }
|
2617 | else
|
2618 | {
|
2619 | /* Disable the selected ETHERNET MMC interrupts */
|
2620 | ETH->MMCRIMR |= ETH_MMC_IT;
|
2621 | }
|
2622 | }
|
2623 | else
|
2624 | {
|
2625 | /* ETHERNET MMC Tx interrupts selected */
|
2626 | if (NewState != DISABLE)
|
2627 | {
|
2628 | /* Enable the selected ETHERNET MMC interrupts */
|
2629 | ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT);
|
2630 | }
|
2631 | else
|
2632 | {
|
2633 | /* Disable the selected ETHERNET MMC interrupts */
|
2634 | ETH->MMCTIMR |= ETH_MMC_IT;
|
2635 | }
|
2636 | }
|
2637 | }
|
2638 |
|
2639 | /**
|
2640 | * @brief Checks whether the specified ETHERNET MMC IT is set or not.
|
2641 | * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt.
|
2642 | * This parameter can be one of the following values:
|
2643 | * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value
|
2644 | * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value
|
2645 | * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value
|
2646 | * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value
|
2647 | * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value
|
2648 | * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value
|
2649 | * @retval The value of ETHERNET MMC IT (SET or RESET).
|
2650 | */
|
2651 | ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT)
|
2652 | {
|
2653 | ITStatus bitstatus = RESET;
|
2654 | /* Check the parameters */
|
2655 | assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT));
|
2656 |
|
2657 | if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
|
2658 | {
|
2659 | /* ETHERNET MMC Rx interrupts selected */
|
2660 | /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occurred */
|
2661 | if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) == (uint32_t)RESET))
|
2662 | {
|
2663 | bitstatus = SET;
|
2664 | }
|
2665 | else
|
2666 | {
|
2667 | bitstatus = RESET;
|
2668 | }
|
2669 | }
|
2670 | else
|
2671 | {
|
2672 | /* ETHERNET MMC Tx interrupts selected */
|
2673 | /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occurred */
|
2674 | if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) == (uint32_t)RESET))
|
2675 | {
|
2676 | bitstatus = SET;
|
2677 | }
|
2678 | else
|
2679 | {
|
2680 | bitstatus = RESET;
|
2681 | }
|
2682 | }
|
2683 |
|
2684 | return bitstatus;
|
2685 | }
|
2686 |
|
2687 | /**
|
2688 | * @brief Get the specified ETHERNET MMC register value.
|
2689 | * @param ETH_MMCReg: specifies the ETHERNET MMC register.
|
2690 | * This parameter can be one of the following values:
|
2691 | * @arg ETH_MMCCR : MMC CR register
|
2692 | * @arg ETH_MMCRIR : MMC RIR register
|
2693 | * @arg ETH_MMCTIR : MMC TIR register
|
2694 | * @arg ETH_MMCRIMR : MMC RIMR register
|
2695 | * @arg ETH_MMCTIMR : MMC TIMR register
|
2696 | * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register
|
2697 | * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register
|
2698 | * @arg ETH_MMCTGFCR : MMC TGFCR register
|
2699 | * @arg ETH_MMCRFCECR : MMC RFCECR register
|
2700 | * @arg ETH_MMCRFAECR : MMC RFAECR register
|
2701 | * @arg ETH_MMCRGUFCR : MMC RGUFCRregister
|
2702 | * @retval The value of ETHERNET MMC Register value.
|
2703 | */
|
2704 | uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg)
|
2705 | {
|
2706 | /* Check the parameters */
|
2707 | assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));
|
2708 |
|
2709 | /* Return the selected register value */
|
2710 | return (*(volatile uint32_t *)(ETH_MAC_BASE + ETH_MMCReg));
|
2711 | }
|
2712 |
|
2713 |
|
2714 |
|
2715 | /**
|
2716 | * @}
|
2717 | */
|
2718 |
|
2719 | /**
|
2720 | * @}
|
2721 | */
|