1 | /**
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2 | ******************************************************************************
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3 | * @file stm32f4x7_eth.h
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4 | * @author MCD Application Team
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5 | * @version V1.0.0
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6 | * @date 14-October-2011
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7 | * @brief This file contains all the functions prototypes for the Ethernet
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8 | * firmware driver.
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9 | ******************************************************************************
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10 | * @attention
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11 | *
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12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 | *
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19 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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20 | ******************************************************************************
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21 | */
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22 |
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23 | /* Define to prevent recursive inclusion -------------------------------------*/
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24 | #ifndef __STM32F4x7_ETH_H
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25 | #define __STM32F4x7_ETH_H
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26 |
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27 | #ifdef __cplusplus
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28 | extern "C" {
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29 | #endif
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30 |
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31 | /* Includes ------------------------------------------------------------------*/
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32 | #include "stm32f4x7_eth_conf.h"
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33 |
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34 | /** @addtogroup STM32F4x7_ETH_Driver
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35 | * @{
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36 | */
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37 |
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38 | /** @defgroup ETH_Exported_Types
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39 | * @{
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40 | */
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41 |
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42 | /**
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43 | * @brief ETH MAC Init structure definition
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44 | * @note The user should not configure all the ETH_InitTypeDef structure's fields.
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45 | * By calling the ETH_StructInit function the structure�s fields are set to their default values.
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46 | * Only the parameters that will be set to a non-default value should be configured.
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47 | */
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48 | typedef struct {
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49 | /**
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50 | * @brief / * MAC
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51 | */
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52 | uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
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53 | The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
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54 | and the mode (half/full-duplex).
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55 | This parameter can be a value of @ref ETH_AutoNegotiation */
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56 |
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57 | uint32_t ETH_Watchdog; /*!< Selects or not the Watchdog timer
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58 | When enabled, the MAC allows no more then 2048 bytes to be received.
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59 | When disabled, the MAC can receive up to 16384 bytes.
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60 | This parameter can be a value of @ref ETH_watchdog */
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61 |
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62 | uint32_t ETH_Jabber; /*!< Selects or not Jabber timer
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63 | When enabled, the MAC allows no more then 2048 bytes to be sent.
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64 | When disabled, the MAC can send up to 16384 bytes.
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65 | This parameter can be a value of @ref ETH_Jabber */
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66 |
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67 | uint32_t ETH_InterFrameGap; /*!< Selects the minimum IFG between frames during transmission
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68 | This parameter can be a value of @ref ETH_Inter_Frame_Gap */
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69 |
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70 | uint32_t ETH_CarrierSense; /*!< Selects or not the Carrier Sense
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71 | This parameter can be a value of @ref ETH_Carrier_Sense */
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72 |
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73 | uint32_t ETH_Speed; /*!< Sets the Ethernet speed: 10/100 Mbps
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74 | This parameter can be a value of @ref ETH_Speed */
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75 |
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76 | uint32_t ETH_ReceiveOwn; /*!< Selects or not the ReceiveOwn
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77 | ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
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78 | in Half-Duplex mode
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79 | This parameter can be a value of @ref ETH_Receive_Own */
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80 |
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81 | uint32_t ETH_LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode
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82 | This parameter can be a value of @ref ETH_Loop_Back_Mode */
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83 |
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84 | uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
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85 | This parameter can be a value of @ref ETH_Duplex_Mode */
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86 |
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87 | uint32_t ETH_ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
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88 | This parameter can be a value of @ref ETH_Checksum_Offload */
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89 |
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90 | uint32_t ETH_RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
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91 | when a collision occurs (Half-Duplex mode)
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92 | This parameter can be a value of @ref ETH_Retry_Transmission */
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93 |
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94 | uint32_t ETH_AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping
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95 | This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
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96 |
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97 | uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value
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98 | This parameter can be a value of @ref ETH_Back_Off_Limit */
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99 |
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100 | uint32_t ETH_DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode)
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101 | This parameter can be a value of @ref ETH_Deferral_Check */
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102 |
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103 | uint32_t ETH_ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering)
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104 | This parameter can be a value of @ref ETH_Receive_All */
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105 |
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106 | uint32_t ETH_SourceAddrFilter; /*!< Selects the Source Address Filter mode
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107 | This parameter can be a value of @ref ETH_Source_Addr_Filter */
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108 |
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109 | uint32_t ETH_PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
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110 | This parameter can be a value of @ref ETH_Pass_Control_Frames */
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111 |
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112 | uint32_t ETH_BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames
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113 | This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
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114 |
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115 | uint32_t ETH_DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames
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116 | This parameter can be a value of @ref ETH_Destination_Addr_Filter */
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117 |
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118 | uint32_t ETH_PromiscuousMode; /*!< Selects or not the Promiscuous Mode
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119 | This parameter can be a value of @ref ETH_Promiscuous_Mode */
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120 |
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121 | uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
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122 | This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
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123 |
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124 | uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
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125 | This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
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126 |
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127 | uint32_t ETH_HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */
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128 |
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129 | uint32_t ETH_HashTableLow; /*!< This field holds the lower 32 bits of Hash table. */
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130 |
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131 | uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the
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132 | transmit control frame */
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133 |
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134 | uint32_t ETH_ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames
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135 | This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
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136 |
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137 | uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
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138 | automatic retransmission of PAUSE Frame
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139 | This parameter can be a value of @ref ETH_Pause_Low_Threshold */
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140 |
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141 | uint32_t ETH_UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
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142 | unicast address and unique multicast address)
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143 | This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
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144 |
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145 | uint32_t ETH_ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
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146 | disable its transmitter for a specified time (Pause Time)
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147 | This parameter can be a value of @ref ETH_Receive_Flow_Control */
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148 |
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149 | uint32_t ETH_TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
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150 | or the MAC back-pressure operation (Half-Duplex mode)
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151 | This parameter can be a value of @ref ETH_Transmit_Flow_Control */
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152 |
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153 | uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
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154 | comparison and filtering
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155 | This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
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156 |
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157 | uint32_t ETH_VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
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158 |
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159 | /**
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160 | * @brief / * DMA
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161 | */
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162 |
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163 | uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames
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164 | This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
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165 |
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166 | uint32_t ETH_ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode
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167 | This parameter can be a value of @ref ETH_Receive_Store_Forward */
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168 |
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169 | uint32_t ETH_FlushReceivedFrame; /*!< Enables or disables the flushing of received frames
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170 | This parameter can be a value of @ref ETH_Flush_Received_Frame */
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171 |
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172 | uint32_t ETH_TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode
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173 | This parameter can be a value of @ref ETH_Transmit_Store_Forward */
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174 |
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175 | uint32_t ETH_TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control
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176 | This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
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177 |
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178 | uint32_t ETH_ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames
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179 | This parameter can be a value of @ref ETH_Forward_Error_Frames */
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180 |
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181 | uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
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182 | and length less than 64 bytes) including pad-bytes and CRC)
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183 | This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
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184 |
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185 | uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO
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186 | This parameter can be a value of @ref ETH_Receive_Threshold_Control */
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187 |
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188 | uint32_t ETH_SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
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189 | frame of Transmit data even before obtaining the status for the first frame.
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190 | This parameter can be a value of @ref ETH_Second_Frame_Operate */
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191 |
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192 | uint32_t ETH_AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats
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193 | This parameter can be a value of @ref ETH_Address_Aligned_Beats */
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194 |
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195 | uint32_t ETH_FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers
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196 | This parameter can be a value of @ref ETH_Fixed_Burst */
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197 |
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198 | uint32_t ETH_RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction
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199 | This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
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200 |
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201 | uint32_t ETH_TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction
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202 | This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
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203 |
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204 | uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */
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205 |
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206 | uint32_t ETH_DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration
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207 | This parameter can be a value of @ref ETH_DMA_Arbitration */
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208 | }ETH_InitTypeDef;
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209 |
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210 | /**--------------------------------------------------------------------------**/
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211 | /**
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212 | * @brief DMA descriptors types
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213 | */
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214 | /**--------------------------------------------------------------------------**/
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215 |
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216 | /**
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217 | * @brief ETH DMA Descriptors data structure definition
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218 | */
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219 | typedef struct {
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220 | volatile uint32_t Status; /*!< Status */
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221 | uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
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222 | uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
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223 | uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
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224 | /* Enhanced ETHERNET DMA PTP Descriptors */
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225 | #ifdef USE_ENHANCED_DMA_DESCRIPTORS
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226 | uint32_t ExtendedStatus; /* Extended status for PTP receive descriptor */
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227 | uint32_t Reserved1; /* Reserved */
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228 | uint32_t TimeStampLow; /* Time Stamp Low value for transmit and receive */
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229 | uint32_t TimeStampHigh; /* Time Stamp High value for transmit and receive */
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230 | #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
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231 | } ETH_DMADESCTypeDef;
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232 |
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233 |
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234 | typedef struct{
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235 | u32 length;
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236 | u32 buffer;
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237 | volatile ETH_DMADESCTypeDef *descriptor;
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238 | }FrameTypeDef;
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239 |
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240 |
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241 | typedef struct {
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242 | volatile ETH_DMADESCTypeDef *FS_Rx_Desc; /*!< First Segment Rx Desc */
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243 | volatile ETH_DMADESCTypeDef *LS_Rx_Desc; /*!< Last Segment Rx Desc */
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244 | volatile uint32_t Seg_Count; /*!< Segment count */
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245 | } ETH_DMA_Rx_Frame_infos;
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246 |
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247 |
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248 | /**
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249 | * @}
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250 | */
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251 |
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252 | /** @defgroup ETH_Exported_Constants
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253 | * @{
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254 | */
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255 |
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256 | /**--------------------------------------------------------------------------**/
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257 | /**
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258 | * @brief ETH Frames defines
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259 | */
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260 | /**--------------------------------------------------------------------------**/
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261 |
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262 | /** @defgroup ENET_Buffers_setting
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263 | * @{
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264 | */
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265 | #define ETH_MAX_PACKET_SIZE 1524 /*!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
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266 | #define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
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267 | #define ETH_CRC 4 /*!< Ethernet CRC */
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268 | #define ETH_EXTRA 2 /*!< Extra bytes in some cases */
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269 | #define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */
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270 | #define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */
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271 | #define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */
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272 | #define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */
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273 |
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274 | /* Ethernet driver receive buffers are organized in a chained linked-list, when
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275 | an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
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276 | to the driver receive buffers memory.
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277 |
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278 | Depending on the size of the received ethernet packet and the size of
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279 | each ethernet driver receive buffer, the received packet can take one or more
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280 | ethernet driver receive buffer.
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281 |
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282 | In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
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283 | and the total count of the driver receive buffers ETH_RXBUFNB.
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284 |
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285 | The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
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286 | example, they can be reconfigured in the application layer to fit the application
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287 | needs */
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288 |
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289 | /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
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290 | packet */
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291 | #ifndef ETH_RX_BUF_SIZE
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292 | #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
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293 | #endif
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294 |
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295 | /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
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296 | #ifndef ETH_RXBUFNB
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297 | #define ETH_RXBUFNB 5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
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298 | #endif
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299 |
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300 |
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301 | /* Ethernet driver transmit buffers are organized in a chained linked-list, when
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302 | an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
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303 | driver transmit buffers memory to the TxFIFO.
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304 |
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305 | Depending on the size of the Ethernet packet to be transmitted and the size of
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306 | each ethernet driver transmit buffer, the packet to be transmitted can take
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307 | one or more ethernet driver transmit buffer.
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308 |
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309 | In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
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310 | and the total count of the driver transmit buffers ETH_TXBUFNB.
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311 |
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312 | The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
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313 | example, they can be reconfigured in the application layer to fit the application
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314 | needs */
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315 |
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316 | /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
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317 | packet */
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318 | #ifndef ETH_TX_BUF_SIZE
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319 | #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
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320 | #endif
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321 |
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322 | /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
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323 | #ifndef ETH_TXBUFNB
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324 | #define ETH_TXBUFNB 5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
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325 | #endif
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326 |
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327 | #define ETH_DMARxDesc_FrameLengthShift 16
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328 |
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329 | /**--------------------------------------------------------------------------**/
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330 | /**
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331 | * @brief Ethernet DMA descriptors registers bits definition
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332 | */
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333 | /**--------------------------------------------------------------------------**/
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334 |
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335 | /**
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336 | @code
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337 | DMA Tx Desciptor
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338 | -----------------------------------------------------------------------------------------------
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339 | TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
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340 | -----------------------------------------------------------------------------------------------
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341 | TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
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342 | -----------------------------------------------------------------------------------------------
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343 | TDES2 | Buffer1 Address [31:0] |
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344 | -----------------------------------------------------------------------------------------------
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345 | TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
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346 | -----------------------------------------------------------------------------------------------
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347 | @endcode
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348 | */
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349 |
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350 | /**
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351 | * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
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352 | */
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353 | #define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
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354 | #define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
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355 | #define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */
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356 | #define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */
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357 | #define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */
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358 | #define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */
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359 | #define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
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360 | #define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
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361 | #define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
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362 | #define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
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363 | #define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
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364 | #define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
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365 | #define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
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366 | #define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
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367 | #define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
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368 | #define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
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369 | #define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
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370 | #define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
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371 | #define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
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372 | #define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
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373 | #define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
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374 | #define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
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375 | #define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
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376 | #define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
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377 | #define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
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378 | #define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */
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379 | #define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
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380 | #define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
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381 | #define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
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382 |
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383 | /**
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384 | * @brief Bit definition of TDES1 register
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385 | */
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386 | #define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
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387 | #define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
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388 |
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389 | /**
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390 | * @brief Bit definition of TDES2 register
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391 | */
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392 | #define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
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393 |
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394 | /**
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395 | * @brief Bit definition of TDES3 register
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396 | */
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397 | #define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
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398 |
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399 | /*---------------------------------------------------------------------------------------------
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400 | TDES6 | Transmit Time Stamp Low [31:0] |
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401 | -----------------------------------------------------------------------------------------------
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402 | TDES7 | Transmit Time Stamp High [31:0] |
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403 | ----------------------------------------------------------------------------------------------*/
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404 |
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405 | /* Bit definition of TDES6 register */
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406 | #define ETH_DMAPTPTxDesc_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
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407 |
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408 | /* Bit definition of TDES7 register */
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409 | #define ETH_DMAPTPTxDesc_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
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410 |
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411 | /**
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412 | * @}
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413 | */
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414 |
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415 |
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416 | /** @defgroup DMA_Rx_descriptor
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417 | * @{
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418 | */
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419 |
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420 | /**
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421 | @code
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422 | DMA Rx Descriptor
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423 | --------------------------------------------------------------------------------------------------------------------
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424 | RDES0 | OWN(31) | Status [30:0] |
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425 | ---------------------------------------------------------------------------------------------------------------------
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426 | RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
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427 | ---------------------------------------------------------------------------------------------------------------------
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428 | RDES2 | Buffer1 Address [31:0] |
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429 | ---------------------------------------------------------------------------------------------------------------------
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430 | RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
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431 | ---------------------------------------------------------------------------------------------------------------------
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432 | @endcode
|
433 | */
|
434 |
|
435 | /**
|
436 | * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
|
437 | */
|
438 | #define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
|
439 | #define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
|
440 | #define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
|
441 | #define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
|
442 | #define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
|
443 | #define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
|
444 | #define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
|
445 | #define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
|
446 | #define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
|
447 | #define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
|
448 | #define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
|
449 | #define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
|
450 | #define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
|
451 | #define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
|
452 | #define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
|
453 | #define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
|
454 | #define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
|
455 | #define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */
|
456 | #define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
|
457 |
|
458 | /**
|
459 | * @brief Bit definition of RDES1 register
|
460 | */
|
461 | #define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
|
462 | #define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
|
463 | #define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
|
464 | #define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
|
465 | #define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
|
466 |
|
467 | /**
|
468 | * @brief Bit definition of RDES2 register
|
469 | */
|
470 | #define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
|
471 |
|
472 | /**
|
473 | * @brief Bit definition of RDES3 register
|
474 | */
|
475 | #define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
|
476 |
|
477 | /*---------------------------------------------------------------------------------------------------------------------
|
478 | RDES4 | Reserved[31:15] | Extended Status [14:0] |
|
479 | ---------------------------------------------------------------------------------------------------------------------
|
480 | RDES5 | Reserved[31:0] |
|
481 | ---------------------------------------------------------------------------------------------------------------------
|
482 | RDES6 | Receive Time Stamp Low [31:0] |
|
483 | ---------------------------------------------------------------------------------------------------------------------
|
484 | RDES7 | Receive Time Stamp High [31:0] |
|
485 | --------------------------------------------------------------------------------------------------------------------*/
|
486 |
|
487 | /* Bit definition of RDES4 register */
|
488 | #define ETH_DMAPTPRxDesc_PTPV ((uint32_t)0x00002000) /* PTP Version */
|
489 | #define ETH_DMAPTPRxDesc_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
|
490 | #define ETH_DMAPTPRxDesc_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
|
491 | #define ETH_DMAPTPRxDesc_PTPMT_Sync ((uint32_t)0x00000100) /* SYNC message (all clock types) */
|
492 | #define ETH_DMAPTPRxDesc_PTPMT_FollowUp ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
|
493 | #define ETH_DMAPTPRxDesc_PTPMT_DelayReq ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
|
494 | #define ETH_DMAPTPRxDesc_PTPMT_DelayResp ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
|
495 | #define ETH_DMAPTPRxDesc_PTPMT_PdelayReq_Announce ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
|
496 | #define ETH_DMAPTPRxDesc_PTPMT_PdelayResp_Manag ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
|
497 | #define ETH_DMAPTPRxDesc_PTPMT_PdelayRespFollowUp_Signal ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
|
498 | #define ETH_DMAPTPRxDesc_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
|
499 | #define ETH_DMAPTPRxDesc_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
|
500 | #define ETH_DMAPTPRxDesc_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
|
501 | #define ETH_DMAPTPRxDesc_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
|
502 | #define ETH_DMAPTPRxDesc_IPHE ((uint32_t)0x00000008) /* IP Header Error */
|
503 | #define ETH_DMAPTPRxDesc_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
|
504 | #define ETH_DMAPTPRxDesc_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
|
505 | #define ETH_DMAPTPRxDesc_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
|
506 | #define ETH_DMAPTPRxDesc_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
|
507 |
|
508 | /* Bit definition of RDES6 register */
|
509 | #define ETH_DMAPTPRxDesc_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
|
510 |
|
511 | /* Bit definition of RDES7 register */
|
512 | #define ETH_DMAPTPRxDesc_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
|
513 |
|
514 |
|
515 | /**--------------------------------------------------------------------------**/
|
516 | /**
|
517 | * @brief Description of common PHY registers
|
518 | */
|
519 | /**--------------------------------------------------------------------------**/
|
520 |
|
521 | /**
|
522 | * @}
|
523 | */
|
524 |
|
525 | /** @defgroup PHY_Read_write_Timeouts
|
526 | * @{
|
527 | */
|
528 | #define PHY_READ_TO ((uint32_t)0x0004FFFF)
|
529 | #define PHY_WRITE_TO ((uint32_t)0x0004FFFF)
|
530 |
|
531 | /**
|
532 | * @}
|
533 | */
|
534 |
|
535 | /** @defgroup PHY_Register_address
|
536 | * @{
|
537 | */
|
538 | #define PHY_BCR 0 /*!< Transceiver Basic Control Register */
|
539 | #define PHY_BSR 1 /*!< Transceiver Basic Status Register */
|
540 |
|
541 | #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
|
542 | #define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
|
543 | ((REG) == PHY_BSR) || \
|
544 | ((REG) == PHY_SR))
|
545 | /**
|
546 | * @}
|
547 | */
|
548 |
|
549 | /** @defgroup PHY_basic_Control_register
|
550 | * @{
|
551 | */
|
552 | #define PHY_Reset ((uint16_t)0x8000) /*!< PHY Reset */
|
553 | #define PHY_Loopback ((uint16_t)0x4000) /*!< Select loop-back mode */
|
554 | #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
|
555 | #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
|
556 | #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
|
557 | #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
|
558 | #define PHY_AutoNegotiation ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
|
559 | #define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
|
560 | #define PHY_Powerdown ((uint16_t)0x0800) /*!< Select the power down mode */
|
561 | #define PHY_Isolate ((uint16_t)0x0400) /*!< Isolate PHY from MII */
|
562 |
|
563 | /**
|
564 | * @}
|
565 | */
|
566 |
|
567 | /** @defgroup PHY_basic_status_register
|
568 | * @{
|
569 | */
|
570 | #define PHY_AutoNego_Complete ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
|
571 | #define PHY_Linked_Status ((uint16_t)0x0004) /*!< Valid link established */
|
572 | #define PHY_Jabber_detection ((uint16_t)0x0002) /*!< Jabber condition detected */
|
573 |
|
574 | /**
|
575 | * @}
|
576 | */
|
577 |
|
578 | /**--------------------------------------------------------------------------**/
|
579 | /**
|
580 | * @brief MAC defines
|
581 | */
|
582 | /**--------------------------------------------------------------------------**/
|
583 |
|
584 | /** @defgroup ETH_AutoNegotiation
|
585 | * @{
|
586 | */
|
587 | #define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001)
|
588 | #define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000)
|
589 | #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
|
590 | ((CMD) == ETH_AutoNegotiation_Disable))
|
591 |
|
592 | /**
|
593 | * @}
|
594 | */
|
595 |
|
596 | /** @defgroup ETH_watchdog
|
597 | * @{
|
598 | */
|
599 | #define ETH_Watchdog_Enable ((uint32_t)0x00000000)
|
600 | #define ETH_Watchdog_Disable ((uint32_t)0x00800000)
|
601 | #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
|
602 | ((CMD) == ETH_Watchdog_Disable))
|
603 |
|
604 | /**
|
605 | * @}
|
606 | */
|
607 |
|
608 | /** @defgroup ETH_Jabber
|
609 | * @{
|
610 | */
|
611 | #define ETH_Jabber_Enable ((uint32_t)0x00000000)
|
612 | #define ETH_Jabber_Disable ((uint32_t)0x00400000)
|
613 | #define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
|
614 | ((CMD) == ETH_Jabber_Disable))
|
615 |
|
616 | /**
|
617 | * @}
|
618 | */
|
619 |
|
620 | /** @defgroup ETH_Inter_Frame_Gap
|
621 | * @{
|
622 | */
|
623 | #define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
|
624 | #define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
|
625 | #define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
|
626 | #define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
|
627 | #define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
|
628 | #define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
|
629 | #define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
|
630 | #define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
|
631 | #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
|
632 | ((GAP) == ETH_InterFrameGap_88Bit) || \
|
633 | ((GAP) == ETH_InterFrameGap_80Bit) || \
|
634 | ((GAP) == ETH_InterFrameGap_72Bit) || \
|
635 | ((GAP) == ETH_InterFrameGap_64Bit) || \
|
636 | ((GAP) == ETH_InterFrameGap_56Bit) || \
|
637 | ((GAP) == ETH_InterFrameGap_48Bit) || \
|
638 | ((GAP) == ETH_InterFrameGap_40Bit))
|
639 |
|
640 | /**
|
641 | * @}
|
642 | */
|
643 |
|
644 | /** @defgroup ETH_Carrier_Sense
|
645 | * @{
|
646 | */
|
647 | #define ETH_CarrierSense_Enable ((uint32_t)0x00000000)
|
648 | #define ETH_CarrierSense_Disable ((uint32_t)0x00010000)
|
649 | #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
|
650 | ((CMD) == ETH_CarrierSense_Disable))
|
651 |
|
652 | /**
|
653 | * @}
|
654 | */
|
655 |
|
656 | /** @defgroup ETH_Speed
|
657 | * @{
|
658 | */
|
659 | #define ETH_Speed_10M ((uint32_t)0x00000000)
|
660 | #define ETH_Speed_100M ((uint32_t)0x00004000)
|
661 | #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
|
662 | ((SPEED) == ETH_Speed_100M))
|
663 |
|
664 | /**
|
665 | * @}
|
666 | */
|
667 |
|
668 | /** @defgroup ETH_Receive_Own
|
669 | * @{
|
670 | */
|
671 | #define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000)
|
672 | #define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000)
|
673 | #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
|
674 | ((CMD) == ETH_ReceiveOwn_Disable))
|
675 |
|
676 | /**
|
677 | * @}
|
678 | */
|
679 |
|
680 | /** @defgroup ETH_Loop_Back_Mode
|
681 | * @{
|
682 | */
|
683 | #define ETH_LoopbackMode_Enable ((uint32_t)0x00001000)
|
684 | #define ETH_LoopbackMode_Disable ((uint32_t)0x00000000)
|
685 | #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
|
686 | ((CMD) == ETH_LoopbackMode_Disable))
|
687 |
|
688 | /**
|
689 | * @}
|
690 | */
|
691 |
|
692 | /** @defgroup ETH_Duplex_Mode
|
693 | * @{
|
694 | */
|
695 | #define ETH_Mode_FullDuplex ((uint32_t)0x00000800)
|
696 | #define ETH_Mode_HalfDuplex ((uint32_t)0x00000000)
|
697 | #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
|
698 | ((MODE) == ETH_Mode_HalfDuplex))
|
699 |
|
700 | /**
|
701 | * @}
|
702 | */
|
703 |
|
704 | /** @defgroup ETH_Checksum_Offload
|
705 | * @{
|
706 | */
|
707 | #define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400)
|
708 | #define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000)
|
709 | #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
|
710 | ((CMD) == ETH_ChecksumOffload_Disable))
|
711 |
|
712 | /**
|
713 | * @}
|
714 | */
|
715 |
|
716 | /** @defgroup ETH_Retry_Transmission
|
717 | * @{
|
718 | */
|
719 | #define ETH_RetryTransmission_Enable ((uint32_t)0x00000000)
|
720 | #define ETH_RetryTransmission_Disable ((uint32_t)0x00000200)
|
721 | #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
|
722 | ((CMD) == ETH_RetryTransmission_Disable))
|
723 |
|
724 | /**
|
725 | * @}
|
726 | */
|
727 |
|
728 | /** @defgroup ETH_Automatic_Pad_CRC_Strip
|
729 | * @{
|
730 | */
|
731 | #define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080)
|
732 | #define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000)
|
733 | #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
|
734 | ((CMD) == ETH_AutomaticPadCRCStrip_Disable))
|
735 |
|
736 | /**
|
737 | * @}
|
738 | */
|
739 |
|
740 | /** @defgroup ETH_Back_Off_Limit
|
741 | * @{
|
742 | */
|
743 | #define ETH_BackOffLimit_10 ((uint32_t)0x00000000)
|
744 | #define ETH_BackOffLimit_8 ((uint32_t)0x00000020)
|
745 | #define ETH_BackOffLimit_4 ((uint32_t)0x00000040)
|
746 | #define ETH_BackOffLimit_1 ((uint32_t)0x00000060)
|
747 | #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
|
748 | ((LIMIT) == ETH_BackOffLimit_8) || \
|
749 | ((LIMIT) == ETH_BackOffLimit_4) || \
|
750 | ((LIMIT) == ETH_BackOffLimit_1))
|
751 |
|
752 | /**
|
753 | * @}
|
754 | */
|
755 |
|
756 | /** @defgroup ETH_Deferral_Check
|
757 | * @{
|
758 | */
|
759 | #define ETH_DeferralCheck_Enable ((uint32_t)0x00000010)
|
760 | #define ETH_DeferralCheck_Disable ((uint32_t)0x00000000)
|
761 | #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
|
762 | ((CMD) == ETH_DeferralCheck_Disable))
|
763 |
|
764 | /**
|
765 | * @}
|
766 | */
|
767 |
|
768 | /** @defgroup ETH_Receive_All
|
769 | * @{
|
770 | */
|
771 | #define ETH_ReceiveAll_Enable ((uint32_t)0x80000000)
|
772 | #define ETH_ReceiveAll_Disable ((uint32_t)0x00000000)
|
773 | #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
|
774 | ((CMD) == ETH_ReceiveAll_Disable))
|
775 |
|
776 | /**
|
777 | * @}
|
778 | */
|
779 |
|
780 | /** @defgroup ETH_Source_Addr_Filter
|
781 | * @{
|
782 | */
|
783 | #define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200)
|
784 | #define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300)
|
785 | #define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000)
|
786 | #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
|
787 | ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \
|
788 | ((CMD) == ETH_SourceAddrFilter_Disable))
|
789 |
|
790 | /**
|
791 | * @}
|
792 | */
|
793 |
|
794 | /** @defgroup ETH_Pass_Control_Frames
|
795 | * @{
|
796 | */
|
797 | #define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
|
798 | #define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
|
799 | #define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
|
800 | #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
|
801 | ((PASS) == ETH_PassControlFrames_ForwardAll) || \
|
802 | ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))
|
803 |
|
804 | /**
|
805 | * @}
|
806 | */
|
807 |
|
808 | /** @defgroup ETH_Broadcast_Frames_Reception
|
809 | * @{
|
810 | */
|
811 | #define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000)
|
812 | #define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020)
|
813 | #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
|
814 | ((CMD) == ETH_BroadcastFramesReception_Disable))
|
815 |
|
816 | /**
|
817 | * @}
|
818 | */
|
819 |
|
820 | /** @defgroup ETH_Destination_Addr_Filter
|
821 | * @{
|
822 | */
|
823 | #define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000)
|
824 | #define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008)
|
825 | #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
|
826 | ((FILTER) == ETH_DestinationAddrFilter_Inverse))
|
827 |
|
828 | /**
|
829 | * @}
|
830 | */
|
831 |
|
832 | /** @defgroup ETH_Promiscuous_Mode
|
833 | * @{
|
834 | */
|
835 | #define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001)
|
836 | #define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000)
|
837 | #define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
|
838 | ((CMD) == ETH_PromiscuousMode_Disable))
|
839 |
|
840 | /**
|
841 | * @}
|
842 | */
|
843 |
|
844 | /** @defgroup ETH_Multicast_Frames_Filter
|
845 | * @{
|
846 | */
|
847 | #define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404)
|
848 | #define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004)
|
849 | #define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000)
|
850 | #define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010)
|
851 | #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
|
852 | ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \
|
853 | ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \
|
854 | ((FILTER) == ETH_MulticastFramesFilter_None))
|
855 |
|
856 |
|
857 | /**
|
858 | * @}
|
859 | */
|
860 |
|
861 | /** @defgroup ETH_Unicast_Frames_Filter
|
862 | * @{
|
863 | */
|
864 | #define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402)
|
865 | #define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002)
|
866 | #define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000)
|
867 | #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
|
868 | ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \
|
869 | ((FILTER) == ETH_UnicastFramesFilter_Perfect))
|
870 |
|
871 | /**
|
872 | * @}
|
873 | */
|
874 |
|
875 | /** @defgroup ETH_Pause_Time
|
876 | * @{
|
877 | */
|
878 | #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
|
879 |
|
880 | /**
|
881 | * @}
|
882 | */
|
883 |
|
884 | /** @defgroup ETH_Zero_Quanta_Pause
|
885 | * @{
|
886 | */
|
887 | #define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000)
|
888 | #define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080)
|
889 | #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \
|
890 | ((CMD) == ETH_ZeroQuantaPause_Disable))
|
891 | /**
|
892 | * @}
|
893 | */
|
894 |
|
895 | /** @defgroup ETH_Pause_Low_Threshold
|
896 | * @{
|
897 | */
|
898 | #define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
|
899 | #define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
|
900 | #define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
|
901 | #define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
|
902 | #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
|
903 | ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \
|
904 | ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \
|
905 | ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))
|
906 |
|
907 | /**
|
908 | * @}
|
909 | */
|
910 |
|
911 | /** @defgroup ETH_Unicast_Pause_Frame_Detect
|
912 | * @{
|
913 | */
|
914 | #define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008)
|
915 | #define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000)
|
916 | #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
|
917 | ((CMD) == ETH_UnicastPauseFrameDetect_Disable))
|
918 |
|
919 | /**
|
920 | * @}
|
921 | */
|
922 |
|
923 | /** @defgroup ETH_Receive_Flow_Control
|
924 | * @{
|
925 | */
|
926 | #define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004)
|
927 | #define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000)
|
928 | #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
|
929 | ((CMD) == ETH_ReceiveFlowControl_Disable))
|
930 |
|
931 | /**
|
932 | * @}
|
933 | */
|
934 |
|
935 | /** @defgroup ETH_Transmit_Flow_Control
|
936 | * @{
|
937 | */
|
938 | #define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002)
|
939 | #define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000)
|
940 | #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
|
941 | ((CMD) == ETH_TransmitFlowControl_Disable))
|
942 |
|
943 | /**
|
944 | * @}
|
945 | */
|
946 |
|
947 | /** @defgroup ETH_VLAN_Tag_Comparison
|
948 | * @{
|
949 | */
|
950 | #define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000)
|
951 | #define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000)
|
952 | #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
|
953 | ((COMPARISON) == ETH_VLANTagComparison_16Bit))
|
954 | #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
|
955 |
|
956 | /**
|
957 | * @}
|
958 | */
|
959 |
|
960 | /** @defgroup ETH_MAC_Flags
|
961 | * @{
|
962 | */
|
963 | #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
|
964 | #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
|
965 | #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
|
966 | #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
|
967 | #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
|
968 | #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
|
969 | ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
|
970 | ((FLAG) == ETH_MAC_FLAG_PMT))
|
971 | /**
|
972 | * @}
|
973 | */
|
974 |
|
975 | /** @defgroup ETH_MAC_Interrupts
|
976 | * @{
|
977 | */
|
978 | #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
|
979 | #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
|
980 | #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
|
981 | #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
|
982 | #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
|
983 | #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
|
984 | #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
|
985 | ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
|
986 | ((IT) == ETH_MAC_IT_PMT))
|
987 | /**
|
988 | * @}
|
989 | */
|
990 |
|
991 | /** @defgroup ETH_MAC_addresses
|
992 | * @{
|
993 | */
|
994 | #define ETH_MAC_Address0 ((uint32_t)0x00000000)
|
995 | #define ETH_MAC_Address1 ((uint32_t)0x00000008)
|
996 | #define ETH_MAC_Address2 ((uint32_t)0x00000010)
|
997 | #define ETH_MAC_Address3 ((uint32_t)0x00000018)
|
998 | #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
|
999 | ((ADDRESS) == ETH_MAC_Address1) || \
|
1000 | ((ADDRESS) == ETH_MAC_Address2) || \
|
1001 | ((ADDRESS) == ETH_MAC_Address3))
|
1002 | #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
|
1003 | ((ADDRESS) == ETH_MAC_Address2) || \
|
1004 | ((ADDRESS) == ETH_MAC_Address3))
|
1005 | /**
|
1006 | * @}
|
1007 | */
|
1008 |
|
1009 | /** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
|
1010 | * @{
|
1011 | */
|
1012 | #define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000)
|
1013 | #define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008)
|
1014 | #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
|
1015 | ((FILTER) == ETH_MAC_AddressFilter_DA))
|
1016 | /**
|
1017 | * @}
|
1018 | */
|
1019 |
|
1020 | /** @defgroup ETH_MAC_addresses_filter_Mask_bytes
|
1021 | * @{
|
1022 | */
|
1023 | #define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
|
1024 | #define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
|
1025 | #define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
|
1026 | #define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
|
1027 | #define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
|
1028 | #define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
|
1029 | #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
|
1030 | ((MASK) == ETH_MAC_AddressMask_Byte5) || \
|
1031 | ((MASK) == ETH_MAC_AddressMask_Byte4) || \
|
1032 | ((MASK) == ETH_MAC_AddressMask_Byte3) || \
|
1033 | ((MASK) == ETH_MAC_AddressMask_Byte2) || \
|
1034 | ((MASK) == ETH_MAC_AddressMask_Byte1))
|
1035 |
|
1036 | /**--------------------------------------------------------------------------**/
|
1037 | /**
|
1038 | * @brief Ethernet DMA Descriptors defines
|
1039 | */
|
1040 | /**--------------------------------------------------------------------------**/
|
1041 | /**
|
1042 | * @}
|
1043 | */
|
1044 |
|
1045 | /** @defgroup ETH_DMA_Tx_descriptor_flags
|
1046 | * @{
|
1047 | */
|
1048 | #define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
|
1049 | ((FLAG) == ETH_DMATxDesc_IC) || \
|
1050 | ((FLAG) == ETH_DMATxDesc_LS) || \
|
1051 | ((FLAG) == ETH_DMATxDesc_FS) || \
|
1052 | ((FLAG) == ETH_DMATxDesc_DC) || \
|
1053 | ((FLAG) == ETH_DMATxDesc_DP) || \
|
1054 | ((FLAG) == ETH_DMATxDesc_TTSE) || \
|
1055 | ((FLAG) == ETH_DMATxDesc_TER) || \
|
1056 | ((FLAG) == ETH_DMATxDesc_TCH) || \
|
1057 | ((FLAG) == ETH_DMATxDesc_TTSS) || \
|
1058 | ((FLAG) == ETH_DMATxDesc_IHE) || \
|
1059 | ((FLAG) == ETH_DMATxDesc_ES) || \
|
1060 | ((FLAG) == ETH_DMATxDesc_JT) || \
|
1061 | ((FLAG) == ETH_DMATxDesc_FF) || \
|
1062 | ((FLAG) == ETH_DMATxDesc_PCE) || \
|
1063 | ((FLAG) == ETH_DMATxDesc_LCA) || \
|
1064 | ((FLAG) == ETH_DMATxDesc_NC) || \
|
1065 | ((FLAG) == ETH_DMATxDesc_LCO) || \
|
1066 | ((FLAG) == ETH_DMATxDesc_EC) || \
|
1067 | ((FLAG) == ETH_DMATxDesc_VF) || \
|
1068 | ((FLAG) == ETH_DMATxDesc_CC) || \
|
1069 | ((FLAG) == ETH_DMATxDesc_ED) || \
|
1070 | ((FLAG) == ETH_DMATxDesc_UF) || \
|
1071 | ((FLAG) == ETH_DMATxDesc_DB))
|
1072 |
|
1073 | /**
|
1074 | * @}
|
1075 | */
|
1076 |
|
1077 | /** @defgroup ETH_DMA_Tx_descriptor_segment
|
1078 | * @{
|
1079 | */
|
1080 | #define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */
|
1081 | #define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */
|
1082 | #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
|
1083 | ((SEGMENT) == ETH_DMATxDesc_FirstSegment))
|
1084 |
|
1085 | /**
|
1086 | * @}
|
1087 | */
|
1088 |
|
1089 | /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
|
1090 | * @{
|
1091 | */
|
1092 | #define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */
|
1093 | #define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
|
1094 | #define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
|
1095 | #define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
|
1096 | #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
|
1097 | ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \
|
1098 | ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \
|
1099 | ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))
|
1100 | /**
|
1101 | * @brief ETH DMA Tx Desciptor buffer size
|
1102 | */
|
1103 | #define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
|
1104 |
|
1105 | /**
|
1106 | * @}
|
1107 | */
|
1108 |
|
1109 | /** @defgroup ETH_DMA_Rx_descriptor_flags
|
1110 | * @{
|
1111 | */
|
1112 | #define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
|
1113 | ((FLAG) == ETH_DMARxDesc_AFM) || \
|
1114 | ((FLAG) == ETH_DMARxDesc_ES) || \
|
1115 | ((FLAG) == ETH_DMARxDesc_DE) || \
|
1116 | ((FLAG) == ETH_DMARxDesc_SAF) || \
|
1117 | ((FLAG) == ETH_DMARxDesc_LE) || \
|
1118 | ((FLAG) == ETH_DMARxDesc_OE) || \
|
1119 | ((FLAG) == ETH_DMARxDesc_VLAN) || \
|
1120 | ((FLAG) == ETH_DMARxDesc_FS) || \
|
1121 | ((FLAG) == ETH_DMARxDesc_LS) || \
|
1122 | ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \
|
1123 | ((FLAG) == ETH_DMARxDesc_LC) || \
|
1124 | ((FLAG) == ETH_DMARxDesc_FT) || \
|
1125 | ((FLAG) == ETH_DMARxDesc_RWT) || \
|
1126 | ((FLAG) == ETH_DMARxDesc_RE) || \
|
1127 | ((FLAG) == ETH_DMARxDesc_DBE) || \
|
1128 | ((FLAG) == ETH_DMARxDesc_CE) || \
|
1129 | ((FLAG) == ETH_DMARxDesc_MAMPCE))
|
1130 |
|
1131 | /* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
|
1132 | #define IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRxDesc_PTPV) || \
|
1133 | ((FLAG) == ETH_DMAPTPRxDesc_PTPFT) || \
|
1134 | ((FLAG) == ETH_DMAPTPRxDesc_PTPMT) || \
|
1135 | ((FLAG) == ETH_DMAPTPRxDesc_IPV6PR) || \
|
1136 | ((FLAG) == ETH_DMAPTPRxDesc_IPV4PR) || \
|
1137 | ((FLAG) == ETH_DMAPTPRxDesc_IPCB) || \
|
1138 | ((FLAG) == ETH_DMAPTPRxDesc_IPPE) || \
|
1139 | ((FLAG) == ETH_DMAPTPRxDesc_IPHE) || \
|
1140 | ((FLAG) == ETH_DMAPTPRxDesc_IPPT))
|
1141 |
|
1142 | /**
|
1143 | * @}
|
1144 | */
|
1145 |
|
1146 | /** @defgroup ETH_DMA_Rx_descriptor_buffers_
|
1147 | * @{
|
1148 | */
|
1149 | #define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
|
1150 | #define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
|
1151 | #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
|
1152 | ((BUFFER) == ETH_DMARxDesc_Buffer2))
|
1153 |
|
1154 | /**--------------------------------------------------------------------------**/
|
1155 | /**
|
1156 | * @brief Ethernet DMA defines
|
1157 | */
|
1158 | /**--------------------------------------------------------------------------**/
|
1159 | /**
|
1160 | * @}
|
1161 | */
|
1162 |
|
1163 | /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
|
1164 | * @{
|
1165 | */
|
1166 | #define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000)
|
1167 | #define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000)
|
1168 | #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
|
1169 | ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))
|
1170 | /**
|
1171 | * @}
|
1172 | */
|
1173 |
|
1174 | /** @defgroup ETH_Receive_Store_Forward
|
1175 | * @{
|
1176 | */
|
1177 | #define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000)
|
1178 | #define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000)
|
1179 | #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
|
1180 | ((CMD) == ETH_ReceiveStoreForward_Disable))
|
1181 | /**
|
1182 | * @}
|
1183 | */
|
1184 |
|
1185 | /** @defgroup ETH_Flush_Received_Frame
|
1186 | * @{
|
1187 | */
|
1188 | #define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000)
|
1189 | #define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000)
|
1190 | #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
|
1191 | ((CMD) == ETH_FlushReceivedFrame_Disable))
|
1192 | /**
|
1193 | * @}
|
1194 | */
|
1195 |
|
1196 | /** @defgroup ETH_Transmit_Store_Forward
|
1197 | * @{
|
1198 | */
|
1199 | #define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000)
|
1200 | #define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000)
|
1201 | #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
|
1202 | ((CMD) == ETH_TransmitStoreForward_Disable))
|
1203 | /**
|
1204 | * @}
|
1205 | */
|
1206 |
|
1207 | /** @defgroup ETH_Transmit_Threshold_Control
|
1208 | * @{
|
1209 | */
|
1210 | #define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
|
1211 | #define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
|
1212 | #define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
|
1213 | #define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
|
1214 | #define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
|
1215 | #define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
|
1216 | #define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
|
1217 | #define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
|
1218 | #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
|
1219 | ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \
|
1220 | ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \
|
1221 | ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \
|
1222 | ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \
|
1223 | ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \
|
1224 | ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \
|
1225 | ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))
|
1226 | /**
|
1227 | * @}
|
1228 | */
|
1229 |
|
1230 | /** @defgroup ETH_Forward_Error_Frames
|
1231 | * @{
|
1232 | */
|
1233 | #define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080)
|
1234 | #define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000)
|
1235 | #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
|
1236 | ((CMD) == ETH_ForwardErrorFrames_Disable))
|
1237 | /**
|
1238 | * @}
|
1239 | */
|
1240 |
|
1241 | /** @defgroup ETH_Forward_Undersized_Good_Frames
|
1242 | * @{
|
1243 | */
|
1244 | #define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040)
|
1245 | #define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000)
|
1246 | #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
|
1247 | ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))
|
1248 |
|
1249 | /**
|
1250 | * @}
|
1251 | */
|
1252 |
|
1253 | /** @defgroup ETH_Receive_Threshold_Control
|
1254 | * @{
|
1255 | */
|
1256 | #define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
|
1257 | #define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
|
1258 | #define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
|
1259 | #define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
|
1260 | #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
|
1261 | ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \
|
1262 | ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \
|
1263 | ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))
|
1264 | /**
|
1265 | * @}
|
1266 | */
|
1267 |
|
1268 | /** @defgroup ETH_Second_Frame_Operate
|
1269 | * @{
|
1270 | */
|
1271 | #define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004)
|
1272 | #define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000)
|
1273 | #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
|
1274 | ((CMD) == ETH_SecondFrameOperate_Disable))
|
1275 |
|
1276 | /**
|
1277 | * @}
|
1278 | */
|
1279 |
|
1280 | /** @defgroup ETH_Address_Aligned_Beats
|
1281 | * @{
|
1282 | */
|
1283 | #define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000)
|
1284 | #define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000)
|
1285 | #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
|
1286 | ((CMD) == ETH_AddressAlignedBeats_Disable))
|
1287 |
|
1288 | /**
|
1289 | * @}
|
1290 | */
|
1291 |
|
1292 | /** @defgroup ETH_Fixed_Burst
|
1293 | * @{
|
1294 | */
|
1295 | #define ETH_FixedBurst_Enable ((uint32_t)0x00010000)
|
1296 | #define ETH_FixedBurst_Disable ((uint32_t)0x00000000)
|
1297 | #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
|
1298 | ((CMD) == ETH_FixedBurst_Disable))
|
1299 |
|
1300 | /**
|
1301 | * @}
|
1302 | */
|
1303 |
|
1304 | /** @defgroup ETH_Rx_DMA_Burst_Length
|
1305 | * @{
|
1306 | */
|
1307 | #define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
|
1308 | #define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
|
1309 | #define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
|
1310 | #define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
|
1311 | #define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
|
1312 | #define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
|
1313 | #define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
|
1314 | #define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
|
1315 | #define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
|
1316 | #define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
|
1317 | #define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
|
1318 | #define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
|
1319 |
|
1320 | #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
|
1321 | ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \
|
1322 | ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \
|
1323 | ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \
|
1324 | ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \
|
1325 | ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \
|
1326 | ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \
|
1327 | ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \
|
1328 | ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \
|
1329 | ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \
|
1330 | ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \
|
1331 | ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))
|
1332 |
|
1333 | /**
|
1334 | * @}
|
1335 | */
|
1336 |
|
1337 | /** @defgroup ETH_Tx_DMA_Burst_Length
|
1338 | * @{
|
1339 | */
|
1340 | #define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
|
1341 | #define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
|
1342 | #define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
|
1343 | #define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
|
1344 | #define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
|
1345 | #define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
|
1346 | #define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
|
1347 | #define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
|
1348 | #define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
|
1349 | #define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
|
1350 | #define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
|
1351 | #define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
|
1352 |
|
1353 | #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
|
1354 | ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \
|
1355 | ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \
|
1356 | ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \
|
1357 | ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \
|
1358 | ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \
|
1359 | ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \
|
1360 | ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \
|
1361 | ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \
|
1362 | ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \
|
1363 | ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \
|
1364 | ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))
|
1365 | /**
|
1366 | * @brief ETH DMA Descriptor SkipLength
|
1367 | */
|
1368 | #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
|
1369 |
|
1370 | /**
|
1371 | * @}
|
1372 | */
|
1373 |
|
1374 | /** @defgroup ETH_DMA_Arbitration
|
1375 | * @{
|
1376 | */
|
1377 | #define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000)
|
1378 | #define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000)
|
1379 | #define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000)
|
1380 | #define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000)
|
1381 | #define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002)
|
1382 | #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
|
1383 | ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \
|
1384 | ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \
|
1385 | ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \
|
1386 | ((RATIO) == ETH_DMAArbitration_RxPriorTx))
|
1387 | /**
|
1388 | * @}
|
1389 | */
|
1390 |
|
1391 | /** @defgroup ETH_DMA_Flags
|
1392 | * @{
|
1393 | */
|
1394 | #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
|
1395 | #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
|
1396 | #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
|
1397 | #define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
|
1398 | #define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
|
1399 | #define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
|
1400 | #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
|
1401 | #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
|
1402 | #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
|
1403 | #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
|
1404 | #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
|
1405 | #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
|
1406 | #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
|
1407 | #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
|
1408 | #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
|
1409 | #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
|
1410 | #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
|
1411 | #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
|
1412 | #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
|
1413 | #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
|
1414 | #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
|
1415 |
|
1416 | #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00))
|
1417 | #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
|
1418 | ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \
|
1419 | ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \
|
1420 | ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
|
1421 | ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
|
1422 | ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
|
1423 | ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
|
1424 | ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
|
1425 | ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
|
1426 | ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
|
1427 | ((FLAG) == ETH_DMA_FLAG_T))
|
1428 | /**
|
1429 | * @}
|
1430 | */
|
1431 |
|
1432 | /** @defgroup ETH_DMA_Interrupts
|
1433 | * @{
|
1434 | */
|
1435 | #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
|
1436 | #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
|
1437 | #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
|
1438 | #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
|
1439 | #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
|
1440 | #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
|
1441 | #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
|
1442 | #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
|
1443 | #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
|
1444 | #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
|
1445 | #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
|
1446 | #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
|
1447 | #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
|
1448 | #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
|
1449 | #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
|
1450 | #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
|
1451 | #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
|
1452 | #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
|
1453 |
|
1454 | #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00))
|
1455 | #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
|
1456 | ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
|
1457 | ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
|
1458 | ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
|
1459 | ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
|
1460 | ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
|
1461 | ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
|
1462 | ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
|
1463 | ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
|
1464 |
|
1465 | /**
|
1466 | * @}
|
1467 | */
|
1468 |
|
1469 | /** @defgroup ETH_DMA_transmit_process_state_
|
1470 | * @{
|
1471 | */
|
1472 | #define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
|
1473 | #define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
|
1474 | #define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */
|
1475 | #define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
|
1476 | #define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
|
1477 | #define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
|
1478 |
|
1479 | /**
|
1480 | * @}
|
1481 | */
|
1482 |
|
1483 |
|
1484 | /** @defgroup ETH_DMA_receive_process_state_
|
1485 | * @{
|
1486 | */
|
1487 | #define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
|
1488 | #define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
|
1489 | #define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */
|
1490 | #define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
|
1491 | #define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
|
1492 | #define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
|
1493 |
|
1494 | /**
|
1495 | * @}
|
1496 | */
|
1497 |
|
1498 | /** @defgroup ETH_DMA_overflow_
|
1499 | * @{
|
1500 | */
|
1501 | #define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
|
1502 | #define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
|
1503 | #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
|
1504 | ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))
|
1505 |
|
1506 | /**--------------------------------------------------------------------------**/
|
1507 | /**
|
1508 | * @brief Ethernet PMT defines
|
1509 | */
|
1510 | /**--------------------------------------------------------------------------**/
|
1511 | /**
|
1512 | * @}
|
1513 | */
|
1514 |
|
1515 | /** @defgroup ETH_PMT_Flags
|
1516 | * @{
|
1517 | */
|
1518 | #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
|
1519 | #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
|
1520 | #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
|
1521 | #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
|
1522 | ((FLAG) == ETH_PMT_FLAG_MPR))
|
1523 |
|
1524 | /**--------------------------------------------------------------------------**/
|
1525 | /**
|
1526 | * @brief Ethernet MMC defines
|
1527 | */
|
1528 | /**--------------------------------------------------------------------------**/
|
1529 | /**
|
1530 | * @}
|
1531 | */
|
1532 |
|
1533 | /** @defgroup ETH_MMC_Tx_Interrupts
|
1534 | * @{
|
1535 | */
|
1536 | #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
|
1537 | #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
|
1538 | #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
|
1539 |
|
1540 | /**
|
1541 | * @}
|
1542 | */
|
1543 |
|
1544 | /** @defgroup ETH_MMC_Rx_Interrupts
|
1545 | * @{
|
1546 | */
|
1547 | #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
|
1548 | #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
|
1549 | #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
|
1550 | #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
|
1551 | ((IT) != 0x00))
|
1552 | #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
|
1553 | ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
|
1554 | ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
|
1555 | /**
|
1556 | * @}
|
1557 | */
|
1558 |
|
1559 | /** @defgroup ETH_MMC_Registers
|
1560 | * @{
|
1561 | */
|
1562 | #define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */
|
1563 | #define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */
|
1564 | #define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */
|
1565 | #define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */
|
1566 | #define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */
|
1567 | #define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */
|
1568 | #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */
|
1569 | #define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */
|
1570 | #define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */
|
1571 | #define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */
|
1572 | #define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */
|
1573 |
|
1574 | /**
|
1575 | * @brief ETH MMC registers
|
1576 | */
|
1577 | #define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
|
1578 | ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
|
1579 | ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
|
1580 | ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
|
1581 | ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
|
1582 | ((REG) == ETH_MMCRGUFCR))
|
1583 |
|
1584 | /**--------------------------------------------------------------------------**/
|
1585 | /**
|
1586 | * @brief Ethernet PTP defines
|
1587 | */
|
1588 | /**--------------------------------------------------------------------------**/
|
1589 | /**
|
1590 | * @}
|
1591 | */
|
1592 |
|
1593 | /** @defgroup ETH_PTP_time_update_method
|
1594 | * @{
|
1595 | */
|
1596 | #define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */
|
1597 | #define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */
|
1598 | #define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
|
1599 | ((UPDATE) == ETH_PTP_CoarseUpdate))
|
1600 |
|
1601 | /**
|
1602 | * @}
|
1603 | */
|
1604 |
|
1605 |
|
1606 | /** @defgroup ETH_PTP_Flags
|
1607 | * @{
|
1608 | */
|
1609 | #define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */
|
1610 | #define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */
|
1611 | #define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */
|
1612 | #define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */
|
1613 |
|
1614 | #define ETH_PTP_FLAG_TSTTR ((uint32_t)0x10000002) /* Time stamp target time reached */
|
1615 | #define ETH_PTP_FLAG_TSSO ((uint32_t)0x10000001) /* Time stamp seconds overflow */
|
1616 |
|
1617 | #define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
|
1618 | ((FLAG) == ETH_PTP_FLAG_TSITE) || \
|
1619 | ((FLAG) == ETH_PTP_FLAG_TSSTU) || \
|
1620 | ((FLAG) == ETH_PTP_FLAG_TSSTI) || \
|
1621 | ((FLAG) == ETH_PTP_FLAG_TSTTR) || \
|
1622 | ((FLAG) == ETH_PTP_FLAG_TSSO))
|
1623 |
|
1624 | /**
|
1625 | * @brief ETH PTP subsecond increment
|
1626 | */
|
1627 | #define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)
|
1628 |
|
1629 | /**
|
1630 | * @}
|
1631 | */
|
1632 |
|
1633 |
|
1634 | /** @defgroup ETH_PTP_time_sign
|
1635 | * @{
|
1636 | */
|
1637 | #define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */
|
1638 | #define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */
|
1639 | #define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
|
1640 | ((SIGN) == ETH_PTP_NegativeTime))
|
1641 |
|
1642 | /**
|
1643 | * @brief ETH PTP time stamp low update
|
1644 | */
|
1645 | #define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)
|
1646 |
|
1647 | /**
|
1648 | * @brief ETH PTP registers
|
1649 | */
|
1650 | #define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */
|
1651 | #define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */
|
1652 | #define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */
|
1653 | #define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */
|
1654 | #define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */
|
1655 | #define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */
|
1656 | #define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */
|
1657 | #define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */
|
1658 | #define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */
|
1659 |
|
1660 | #define ETH_PTPTSSR ((uint32_t)0x00000728) /* PTP TSSR register */
|
1661 |
|
1662 | #define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
|
1663 | ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \
|
1664 | ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \
|
1665 | ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \
|
1666 | ((REG) == ETH_PTPTTLR) || ((REG) == ETH_PTPTSSR))
|
1667 |
|
1668 | /**
|
1669 | * @brief ETHERNET PTP clock
|
1670 | */
|
1671 | #define ETH_PTP_OrdinaryClock ((uint32_t)0x00000000) /* Ordinary Clock */
|
1672 | #define ETH_PTP_BoundaryClock ((uint32_t)0x00010000) /* Boundary Clock */
|
1673 | #define ETH_PTP_EndToEndTransparentClock ((uint32_t)0x00020000) /* End To End Transparent Clock */
|
1674 | #define ETH_PTP_PeerToPeerTransparentClock ((uint32_t)0x00030000) /* Peer To Peer Transparent Clock */
|
1675 |
|
1676 | #define IS_ETH_PTP_TYPE_CLOCK(CLOCK) (((CLOCK) == ETH_PTP_OrdinaryClock) || \
|
1677 | ((CLOCK) == ETH_PTP_BoundaryClock) || \
|
1678 | ((CLOCK) == ETH_PTP_EndToEndTransparentClock) || \
|
1679 | ((CLOCK) == ETH_PTP_PeerToPeerTransparentClock))
|
1680 | /**
|
1681 | * @brief ETHERNET snapshot
|
1682 | */
|
1683 | #define ETH_PTP_SnapshotMasterMessage ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
|
1684 | #define ETH_PTP_SnapshotEventMessage ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
|
1685 | #define ETH_PTP_SnapshotIPV4Frames ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
|
1686 | #define ETH_PTP_SnapshotIPV6Frames ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
|
1687 | #define ETH_PTP_SnapshotPTPOverEthernetFrames ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
|
1688 | #define ETH_PTP_SnapshotAllReceivedFrames ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
|
1689 |
|
1690 | #define IS_ETH_PTP_SNAPSHOT(SNAPSHOT) (((SNAPSHOT) == ETH_PTP_SnapshotMasterMessage) || \
|
1691 | ((SNAPSHOT) == ETH_PTP_SnapshotEventMessage) || \
|
1692 | ((SNAPSHOT) == ETH_PTP_SnapshotIPV4Frames) || \
|
1693 | ((SNAPSHOT) == ETH_PTP_SnapshotIPV6Frames) || \
|
1694 | ((SNAPSHOT) == ETH_PTP_SnapshotPTPOverEthernetFrames) || \
|
1695 | ((SNAPSHOT) == ETH_PTP_SnapshotAllReceivedFrames))
|
1696 |
|
1697 | /**
|
1698 | * @}
|
1699 | */
|
1700 | /* ETHERNET MAC address offsets */
|
1701 | #define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */
|
1702 | #define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */
|
1703 |
|
1704 | /* ETHERNET MACMIIAR register Mask */
|
1705 | #define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
|
1706 |
|
1707 | /* ETHERNET MACCR register Mask */
|
1708 | #define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
|
1709 |
|
1710 | /* ETHERNET MACFCR register Mask */
|
1711 | #define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
|
1712 |
|
1713 |
|
1714 | /* ETHERNET DMAOMR register Mask */
|
1715 | #define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
|
1716 |
|
1717 |
|
1718 | /* ETHERNET Remote Wake-up frame register length */
|
1719 | #define ETH_WAKEUP_REGISTER_LENGTH 8
|
1720 |
|
1721 | /* ETHERNET Missed frames counter Shift */
|
1722 | #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
|
1723 |
|
1724 | /* ETHERNET DMA Tx descriptors Collision Count Shift */
|
1725 | #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3
|
1726 |
|
1727 | /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
|
1728 | #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16
|
1729 |
|
1730 | /* ETHERNET DMA Rx descriptors Frame Length Shift */
|
1731 | #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16
|
1732 |
|
1733 | /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
|
1734 | #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16
|
1735 |
|
1736 | /* ETHERNET errors */
|
1737 | #define ETH_ERROR ((uint32_t)0)
|
1738 | #define ETH_SUCCESS ((uint32_t)1)
|
1739 |
|
1740 | /**
|
1741 | * @}
|
1742 | */
|
1743 |
|
1744 | /** @defgroup ETH_Exported_Macros
|
1745 | * @{
|
1746 | */
|
1747 | /**
|
1748 | * @}
|
1749 | */
|
1750 |
|
1751 | /** @defgroup ETH_Exported_Functions
|
1752 | * @{
|
1753 | */
|
1754 | void ETH_DeInit(void);
|
1755 | uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress);
|
1756 | void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
|
1757 | void ETH_SoftwareReset(void);
|
1758 | FlagStatus ETH_GetSoftwareResetStatus(void);
|
1759 | void ETH_Start(void);
|
1760 | void ETH_Stop(void);
|
1761 | uint32_t ETH_GetRxPktSize(ETH_DMADESCTypeDef *DMARxDesc);
|
1762 |
|
1763 |
|
1764 | #ifdef USE_ENHANCED_DMA_DESCRIPTORS
|
1765 | void ETH_EnhancedDescriptorCmd(FunctionalState NewState);
|
1766 | #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
|
1767 |
|
1768 | /**
|
1769 | * @brief PHY
|
1770 | */
|
1771 | uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg);
|
1772 | uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue);
|
1773 | uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState);
|
1774 |
|
1775 | /**
|
1776 | * @brief MAC
|
1777 | */
|
1778 | void ETH_MACTransmissionCmd(FunctionalState NewState);
|
1779 | void ETH_MACReceptionCmd(FunctionalState NewState);
|
1780 | FlagStatus ETH_GetFlowControlBusyStatus(void);
|
1781 | void ETH_InitiatePauseControlFrame(void);
|
1782 | void ETH_BackPressureActivationCmd(FunctionalState NewState);
|
1783 | FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG);
|
1784 | ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT);
|
1785 | void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState);
|
1786 | void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr);
|
1787 | void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr);
|
1788 | void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState);
|
1789 | void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter);
|
1790 | void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte);
|
1791 |
|
1792 | /**
|
1793 | * @brief DMA Tx/Rx descriptors
|
1794 | */
|
1795 | void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
|
1796 | void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
|
1797 | uint32_t ETH_CheckFrameReceived(void);
|
1798 | uint32_t ETH_Prepare_Transmit_Descriptors(u16 FrameLength);
|
1799 | FrameTypeDef ETH_Get_Received_Frame(void);
|
1800 | FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag);
|
1801 | uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
|
1802 | void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
|
1803 | void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
1804 | void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment);
|
1805 | void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);
|
1806 | void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
1807 | void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
1808 | void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
1809 | void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2);
|
1810 | FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag);
|
1811 | #ifdef USE_ENHANCED_DMA_DESCRIPTORS
|
1812 | FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag);
|
1813 | #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
|
1814 | void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
|
1815 | uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
|
1816 | void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
|
1817 | void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
|
1818 | uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer);
|
1819 | FrameTypeDef ETH_Get_Received_Frame_interrupt(void);
|
1820 | /**
|
1821 | * @brief DMA
|
1822 | */
|
1823 | FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG);
|
1824 | void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG);
|
1825 | ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT);
|
1826 | void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT);
|
1827 | uint32_t ETH_GetTransmitProcessState(void);
|
1828 | uint32_t ETH_GetReceiveProcessState(void);
|
1829 | void ETH_FlushTransmitFIFO(void);
|
1830 | FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
|
1831 | void ETH_DMATransmissionCmd(FunctionalState NewState);
|
1832 | void ETH_DMAReceptionCmd(FunctionalState NewState);
|
1833 | void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState);
|
1834 | FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow);
|
1835 | uint32_t ETH_GetRxOverflowMissedFrameCounter(void);
|
1836 | uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);
|
1837 | uint32_t ETH_GetCurrentTxDescStartAddress(void);
|
1838 | uint32_t ETH_GetCurrentRxDescStartAddress(void);
|
1839 | uint32_t ETH_GetCurrentTxBufferAddress(void);
|
1840 | uint32_t ETH_GetCurrentRxBufferAddress(void);
|
1841 | void ETH_ResumeDMATransmission(void);
|
1842 | void ETH_ResumeDMAReception(void);
|
1843 | void ETH_SetReceiveWatchdogTimer(uint8_t Value);
|
1844 |
|
1845 |
|
1846 | /**
|
1847 | * @brief PMT
|
1848 | */
|
1849 | void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
|
1850 | void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer);
|
1851 | void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
|
1852 | FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG);
|
1853 | void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
|
1854 | void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
|
1855 | void ETH_PowerDownCmd(FunctionalState NewState);
|
1856 |
|
1857 | /**
|
1858 | * @brief MMC
|
1859 | */
|
1860 | void ETH_MMCCounterFullPreset(void);
|
1861 | void ETH_MMCCounterHalfPreset(void);
|
1862 | void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
|
1863 | void ETH_MMCResetOnReadCmd(FunctionalState NewState);
|
1864 | void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
|
1865 | void ETH_MMCCountersReset(void);
|
1866 | void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState);
|
1867 | ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT);
|
1868 | uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg);
|
1869 |
|
1870 | #ifdef __cplusplus
|
1871 | }
|
1872 | #endif
|
1873 |
|
1874 | #endif /* __STM32F4x7_ETH_H */
|
1875 | /**
|
1876 | * @}
|
1877 | */
|
1878 |
|
1879 |
|
1880 | /**
|
1881 | * @}
|
1882 | */
|
1883 |
|
1884 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|