1 | /////////////////////////////////////////////////////////////////////////////
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2 | // Modul : dmx.c
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3 | /////////////////////////////////////////////////////////////////////////////
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4 | // Version : 1.0
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5 | // Date : 12.01.2014
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6 | // Comment : First Version
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7 | /////////////////////////////////////////////////////////////////////////////
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8 |
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9 | #include <inttypes.h>
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10 | #include <avr/io.h>
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11 | #include <avr/interrupt.h>
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12 | #include <avr/signal.h>
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13 | #include "dmx.h"
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14 | #include "Basis_DMX.h"
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15 | #include <util/delay.h> //muß nach F_CPU definiert werden !!!
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16 |
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17 |
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18 | #define DMX_Channels 512 //Anzahl der zu empfangenden DMX Kanäle
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19 |
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20 | //Variablen
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21 | uint8_t DMX_State_RX; //DMX Empfangsstaus: 0=Leerlauf, 1=Break Empfangen, 2=Startbyte Empfangen, 3=Startadresse erreicht
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22 | uint16_t DMX_RX_Bytecounter; //Variable für DMX Byte Counter (gezählt von Paket 1) für empfangen
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23 | uint16_t k=0;
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24 | //============================================================================================
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25 | //DMX Inizialisierung
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26 | //Es wird UART 1 verwendet (Txd1)
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27 | //Clock 16 MHZ
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28 | //DMX : 250KHZ,1 Start,8Byte,2Stopp
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29 | //============================================================================================
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30 | void init_DMX(void)
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31 | {
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32 | UBRR1H = 0;
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33 | UBRR1L = 3;
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34 | UCSR1C |= (1<<UCSZ11) | (1<<UCSZ10) | (1<<USBS1); //250kBaud, 2 Stopbits
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35 | UCSR1B = (1<<TXEN1); //Enable Data Register Interrupt,Enable Transmitter 1
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36 | DDRD |= (1<<PD3); //TxD = Output
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37 |
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38 | }
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39 | //============================================================================================
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40 | void transmit_DMX(void)
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41 | {
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42 | uint16_t i;
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43 | UBRR1H = 0;
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44 | UBRR1L = 12; //set 115.2K Baudrate
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45 | while (!(UCSR1A & (1<<UDRE1))) //any data in UDR1?
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46 | ;
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47 | UDR1 = 0; //RESET Frame
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48 | while (!(UCSR1A & (1<<UDRE1)))
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49 | ;
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50 | UBRR1L = 3; //Baud Rate Register = 250KHZ
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51 | UDR1 = 0; //Start
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52 |
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53 | for (i=0;i<512;i++)
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54 | {
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55 | while (!(UCSR1A & (1<<UDRE1)))
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56 | ;
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57 | UDR1 = dmx_buffer[i];
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58 | }
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59 | }
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60 | //============================================================================================
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