1 | //******************************************************************************
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2 | // MSP430F20x2 Demo - ADC10, DTC Sample A2-0, AVcc, Single Sequence, DCO
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3 | //
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4 | // Description: Sample A3/A2/A1 as single sequence with reference to AVcc.
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5 | // Software sets ADC10SC to trigger sample sequence. In Mainloop MSP430 waits
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6 | // in LPM0 to save power until ADC10 conversion complete, ADC10_ISR(DTC) will
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7 | // force exit from any LPMx in Mainloop on reti. ADC10_ISR will force any LPMx
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8 | // exit. ADC10 internal oscillator times sample period (16x) and conversion
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9 | // (13x). DTC transfers conversion code to RAM 200h - 206h. P1.0 set at start
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10 | // of conversion burst, reset on completion.
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11 | //
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12 | // MSP430F20x2
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13 | // -----------------
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14 | // /|\| XIN|-
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15 | // | | |
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16 | // --|RST XOUT|-
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17 | // | |
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18 | // >---|P1.3/A3 P1.0|-->LED
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19 | // >---|P1.2/A2 |
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20 | // >---|P1.1/A1 |
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21 | //
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22 | // L. Westlund
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23 | // Texas Instruments Inc.
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24 | // May 2006
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25 | // Built with IAR Embedded Workbench Version: 3.41A
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26 | //******************************************************************************
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27 | #include "msp430x20x2.h"
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28 |
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29 | void main(void)
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30 | {
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31 | WDTCTL = WDTPW + WDTHOLD; // Stop WDT
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32 | ADC10CTL1 = INCH_3 + CONSEQ_1; // A3/A2/A1, single sequence
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33 | ADC10CTL0 = ADC10SHT_2 + MSC + ADC10ON + ADC10IE;
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34 | ADC10DTC1 = 0x03; // 3 conversions
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35 | ADC10AE0 |= 0x0E; // P1.3,2,1 ADC10 option select
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36 | P1DIR |= 0x01; // Set P1.0 output
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37 |
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38 | for (;;)
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39 | {
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40 | ADC10CTL0 &= ~ENC;
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41 | while (ADC10CTL1 & BUSY); // Wait if ADC10 core is active
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42 | ADC10SA = 0x200; // Data buffer start
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43 | P1OUT |= 0x01; // P1.0 = 1
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44 | ADC10CTL0 |= ENC + ADC10SC; // Sampling and conversion start
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45 | __bis_SR_register(CPUOFF + GIE); // LPM0, ADC10_ISR will force exit
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46 | P1OUT &= ~0x01; // P1.0 = 0
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47 | }
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48 | }
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49 |
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50 | // ADC10 interrupt service routine
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51 | #pragma vector=ADC10_VECTOR
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52 | __interrupt void ADC10_ISR(void)
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53 | {
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54 | __bic_SR_register_on_exit(CPUOFF); // Clear CPUOFF bit from 0(SR)
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55 | }
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