makebits.vhd


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----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    16:39:50 09/13/2007 
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-- Design Name: 
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-- Module Name:    makebits - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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library UNISIM;
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use UNISIM.VComponents.all;
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entity makebits is
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    Port ( 
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    CLK100     :   in    STD_LOGIC;
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    leds      :  out  std_logic_vector(7 downto 0);
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    pcie_rx0_p  :  in    std_logic;  -- data inputs
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    pcie_rx0_n  :  in    std_logic  -- data inputs
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  );
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end makebits;
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architecture Behavioral of makebits is
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-- signals
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  signal tp  :  std_logic;
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  signal incomingbits  :  std_logic_vector(9 downto 0) := "0000000000";
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  signal countincoming  :  std_logic_vector(3 downto 0) := "0000";
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  signal khertz      : std_logic ;
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  signal mhertz      : std_logic ;
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  signal hertz      : std_logic ;
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-- Constants
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-- Components
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  component zeitgeber
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  port (
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    clock : in  STD_LOGIC;
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    mhertz_en : out  STD_LOGIC;
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    khertz_en : out  STD_LOGIC;
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    hertz_en : out  STD_LOGIC
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  );
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  end component;
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begin
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    IBUFDS_inst : IBUFDS 
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    generic map (
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      IOSTANDARD => "LVDS_25",
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      DIFF_TERM => TRUE    -- Differential Termination (Virtex-4/5, Spartan-3E/3A)
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    ) 
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    port map (
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      I => pcie_rx0_p,
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      IB => pcie_rx0_n,
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      O => tp
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    );
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  Clockgen: zeitgeber
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    port map (
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      clock => CLK100,
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      mhertz_en => mhertz,  
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      khertz_en => khertz,
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      hertz_en => hertz
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    );
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  leds <= incomingbits (7 downto 0) when countincoming = "1010" else "00000000";
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  process (mhertz)
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  begin
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    if mhertz'event and mhertz = '1' then
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      incomingbits <= incomingbits(8 downto 0) & tp;
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      countincoming <= countincoming + 1;
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      if countincoming = "1010" then
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        countincoming <= "0000";
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      end if;
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    end if;
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  end process;
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end Behavioral;