1 | /*--------------------------------------------------------------------------
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2 | AT89S8252
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3 |
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4 | Header file for the Atmel AT89S8252.
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5 | Copyright 1996-1997 Keil Elektronik GmbH and Keil Software, Inc.
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6 | All rights reserved.
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7 | --------------------------------------------------------------------------*/
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8 |
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9 | #ifndef AT89S8252_HEADER_FILE
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10 | #define AT89S8252_HEADER_FILE 1
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11 |
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12 | /*------------------------------------------------
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13 | Byte Registers
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14 |
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15 | Note: Only Registers located on addresses that
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16 | are evenly divisible by 8 are bit addressable.
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17 | All other registers use bit masks.
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18 | ------------------------------------------------*/
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19 | sfr P0 = 0x80; /* Port 0 */
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20 | sfr SP = 0x81; /* Stack Pointer */
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21 | sfr DPL = 0x82; /* Data Pointer Low Byte */
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22 | sfr DP0L = 0x82; /* Alternate Definition */
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23 | sfr DPH = 0x83; /* Data Pointer High Byte */
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24 | sfr DP0H = 0x83; /* Alternate Definition */
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25 | sfr DP1L = 0x84; /* Data Pointer 1 Low Byte , different to AT89C52 */
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26 | sfr DP1H = 0x85; /* Data Pointer 1 High Byte , different to AT89C52 */
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27 | sfr SPDR = 0x86; /* SPI Data Register , different to AT89C52 */
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28 | sfr PCON = 0x87; /* Power Control Register */
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29 |
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30 | sfr TCON = 0x88; /* Timer Control Register */
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31 | sfr TMOD = 0x89; /* Timer Mode Control Register */
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32 | sfr TL0 = 0x8A; /* Timer 0 Low Byte */
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33 | sfr TL1 = 0x8B; /* Timer 1 Low Byte */
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34 | sfr TH0 = 0x8C; /* Timer 0 High Byte */
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35 | sfr TH1 = 0x8D; /* Timer 1 High Byte */
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36 |
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37 | sfr P1 = 0x90; /* Port 1 */
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38 | sfr WMCON = 0x96; /* Watchdog and Memory Control Register */
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39 | sfr SCON = 0x98; /* Serial Port Control */
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40 | sfr SBUF = 0x99; /* Serial Port Buffer */
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41 |
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42 | sfr P2 = 0xA0; /* Port 2 */
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43 | sfr IE = 0xA8; /* Interrupt Enable Register 0 */
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44 | sfr SPSR = 0xAA; /* SPI Status Register , different to AT89C52 */
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45 |
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46 | sfr P3 = 0xB0; /* Port 3 */
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47 | sfr IP = 0xB8; /* Interrupt Priority Register */
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48 |
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49 | sfr T2CON = 0xC8; /* Timer 2 Control */
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50 | sfr T2MOD = 0xC9; /* Timer 2 Mode */
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51 | sfr RCAP2L = 0xCA; /* Timer 2 Capture Low Byte */
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52 | sfr RCAP2H = 0xCB; /* Timer 2 Capture High Byte */
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53 | sfr TL2 = 0xCC; /* Timer 2 Low Byte */
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54 | sfr TH2 = 0xCD; /* Timer 2 High Byte */
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55 |
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56 | sfr PSW = 0xD0; /* Program Status Word */
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57 | sfr SPCR = 0xD5; /* SPI Control Register , different to AT89C52 */
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58 |
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59 | sfr ACC = 0xE0; /* Accumulator */
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60 |
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61 | sfr B = 0xF0; /* B Register */
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62 |
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63 | /*------------------------------------------------
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64 | P0 (0x80) Bit Registers
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65 | ------------------------------------------------*/
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66 | sbit P0_0 = 0x80;
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67 | sbit P0_1 = 0x81;
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68 | sbit P0_2 = 0x82;
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69 | sbit P0_3 = 0x83;
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70 | sbit P0_4 = 0x84;
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71 | sbit P0_5 = 0x85;
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72 | sbit P0_6 = 0x86;
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73 | sbit P0_7 = 0x87;
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74 |
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75 | /*------------------------------------------------
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76 | PCON (0x87) Bit Values
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77 | ------------------------------------------------*/
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78 | #define IDL_ 0x01 /* Idle Mode Bit: 1=Active */
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79 |
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80 | #define STOP_ 0x02 /* Stop Mode Bit: 1=Active */
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81 | #define PD_ 0x02 /* Alternate definition */
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82 |
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83 | #define GF0_ 0x04 /* General Purpose Flag 0 */
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84 | #define GF1_ 0x08 /* General Purpose Flag 1 */
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85 | #define SMOD_ 0x80 /* Double Baud Rate Bit for use with Timer 1 */
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86 |
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87 | /*------------------------------------------------
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88 | TCON (0x88) Bit Registers
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89 | ------------------------------------------------*/
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90 | sbit IT0 = 0x88; /* Interrupt 0 Type Control Bit */
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91 | sbit IE0 = 0x89; /* Interrupt 0 Edge Flag */
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92 | sbit IT1 = 0x8A; /* Interrupt 1 Type Control Bit */
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93 | sbit IE1 = 0x8B; /* Interrupt 1 Edge Flag */
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94 | sbit TR0 = 0x8C; /* Timer 0 Run Control Bit */
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95 | sbit TF0 = 0x8D; /* Timer 0 Overflow Flag */
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96 | sbit TR1 = 0x8E; /* Timer 1 Run Control Bit */
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97 | sbit TF1 = 0x8F; /* Timer 1 Overflow Flag */
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98 |
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99 | /*------------------------------------------------
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100 | TMOD (0x89) Bit Values
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101 | ------------------------------------------------*/
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102 | #define T0_M0_ 0x01 /* Timer 0 Mode Bit 0 */
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103 | #define T0_M1_ 0x02 /* Timer 0 Mode Bit 1 */
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104 | #define T0_CT_ 0x04 /* Timer 0 Counter/Timer Select: 0=Counter, 1=Timer */
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105 | #define T0_GATE_ 0x08 /* Timer 0 Gate Control */
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106 |
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107 | #define T1_M0_ 0x10 /* Timer 1 Mode Bit 0 */
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108 | #define T1_M1_ 0x20 /* Timer 1 Mode Bit 1 */
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109 | #define T1_CT_ 0x40 /* Timer 1 Counter/Timer Select: 0=Counter, 1=Timer */
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110 | #define T1_GATE_ 0x80 /* Timer 1 Gate Control */
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111 |
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112 | #define T1_MASK_ 0xF0 /* Timer 0 Mask */
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113 | #define T0_MASK_ 0x0F /* Timer 1 Mask */
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114 |
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115 | /*------------------------------------------------
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116 | P1 (0x90) Bit Registers
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117 | ------------------------------------------------*/
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118 | sbit P1_0 = 0x90;
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119 | sbit P1_1 = 0x91;
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120 | sbit P1_2 = 0x92;
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121 | sbit P1_3 = 0x93;
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122 | sbit P1_4 = 0x94;
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123 | sbit P1_5 = 0x95;
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124 | sbit P1_6 = 0x96;
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125 | sbit P1_7 = 0x97;
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126 |
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127 | sbit T2 = 0x90; /* External input to Timer/Counter 2, clock out */
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128 | sbit T2EX = 0x91; /* Timer/Counter 2 capture/reload trigger & dir ctl */
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129 |
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130 | sbit SS = 0x94; /* SPI: SS - Slave port select input */
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131 | sbit MOSI = 0x95; /* SPI: MOSI - Master data output, slave data input */
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132 | sbit MISO = 0x96; /* SPI: MISO - Master data input, slave data output */
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133 | sbit SCK = 0x97; /* SPI: SCK - Master clock output, slave clock input */
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134 |
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135 | /*------------------------------------------------
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136 | WMCON (0x96) Bit Values
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137 | ------------------------------------------------*/
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138 | #define WDTEN_ 0x01
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139 |
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140 | #define WDTRST_ 0x02 /* Watchdog Timer Reset and EEPROM Ready,/Busy Flag */
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141 | #define EERDY_ 0x02 /* Watchdog Timer Reset and EEPROM Ready,/Busy Flag */
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142 |
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143 | #define DPS_ 0x04 /* Data Pointer Select: 0=DP0, 1=DP1 */
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144 | #define EEMEN_ 0x08 /* Internal EEPROM Access Enable: 1=Enabled */
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145 | #define EEMWE_ 0x10 /* Internal EEPROM Write Enable: 1=Enabled */
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146 | #define PS0_ 0x20 /* Prescaler bit 0 for the Watchdog Timer */
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147 | #define PS1_ 0x40 /* Prescaler bit 1 for the Watchdog Timer */
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148 | #define PS2_ 0x80 /* Prescaler bit 2 for the Watchdog Timer */
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149 | /* 000 = 16ms Timeout */
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150 | /* 001 = 32ms Timeout */
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151 | /* 010 = 64ms Timeout */
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152 | /* 011 = 128ms Timeout */
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153 | /* 100 = 256ms Timeout */
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154 | /* 101 = 512ms Timeout */
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155 | /* 110 = 1024ms Timeout */
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156 | /* 111 = 2048ms Timeout */
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157 |
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158 | /*------------------------------------------------
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159 | SCON (0x98) Bit Registers
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160 | ------------------------------------------------*/
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161 | sbit RI = 0x98; /* Receive Interrupt Flag */
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162 | sbit TI = 0x99; /* Transmit Interrupt Flag */
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163 | sbit RB8 = 0x9A; /* 9th data bit received */
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164 | sbit TB8 = 0x9B; /* 9th data bit to be transmitted in modes 2 & 3 */
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165 | sbit REN = 0x9C; /* Receive Enable */
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166 | sbit SM2 = 0x9D; /* Serial Port Mode Bit 2 */
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167 | sbit SM1 = 0x9E; /* Serial Port Mode Bit 1 */
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168 | sbit SM0 = 0x9F; /* Serial Port Mode Bit 0 */
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169 |
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170 | /*------------------------------------------------
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171 | P2 (0xA0) Bit Registers
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172 | ------------------------------------------------*/
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173 | sbit P2_0 = 0xA0;
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174 | sbit P2_1 = 0xA1;
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175 | sbit P2_2 = 0xA2;
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176 | sbit P2_3 = 0xA3;
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177 | sbit P2_4 = 0xA4;
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178 | sbit P2_5 = 0xA5;
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179 | sbit P2_6 = 0xA6;
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180 | sbit P2_7 = 0xA7;
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181 |
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182 | /*------------------------------------------------
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183 | IE (0xA8) Bit Registers
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184 | ------------------------------------------------*/
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185 | sbit EX0 = 0xA8; /* External Interrupt 0 Enable: 1=Enabled */
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186 | sbit ET0 = 0xA9; /* Timer 0 Interrupt Enable: 1=Enabled */
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187 | sbit EX1 = 0xAA; /* External Interrupt 1 Enable: 1=Enabled */
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188 | sbit ET1 = 0xAB; /* Timer 1 Interrupt Enable: 1=Enabled */
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189 | sbit ES = 0xAC; /* SPI and UART Interrupt Enable: 1=Enabled */
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190 | sbit ET2 = 0xAD; /* Timer 2 Interrupt Enable: 1=Enabled */
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191 |
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192 | sbit EA = 0xAF; /* Global Interrupt Enable: 0=Disable all interrupts */
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193 |
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194 | /*------------------------------------------------
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195 | SPSR (0xAA) Bit Values - Reset Value = 0000.0000
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196 | ------------------------------------------------*/
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197 | #define WCOL_ 0x40 /* SPI Write Collision Flag: 1=Collision */
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198 | #define SPIF_ 0x80 /* SPI Interrupt Flag */
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199 |
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200 | /*------------------------------------------------
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201 | P3 (0xB0) Bit Registers (Mnemonics & Ports)
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202 | ------------------------------------------------*/
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203 | sbit P3_0 = 0xB0;
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204 | sbit P3_1 = 0xB1;
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205 | sbit P3_2 = 0xB2;
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206 | sbit P3_3 = 0xB3;
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207 | sbit P3_4 = 0xB4;
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208 | sbit P3_5 = 0xB5;
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209 | sbit P3_6 = 0xB6;
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210 | sbit P3_7 = 0xB7;
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211 |
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212 | sbit RXD = 0xB0; /* Serial data input */
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213 | sbit TXD = 0xB1; /* Serial data output */
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214 | sbit INT0 = 0xB2; /* External interrupt 0 */
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215 | sbit INT1 = 0xB3; /* External interrupt 1 */
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216 | sbit T0 = 0xB4; /* Timer 0 external input */
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217 | sbit T1 = 0xB5; /* Timer 1 external input */
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218 | sbit WR = 0xB6; /* External data memory write strobe */
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219 | sbit RD = 0xB7; /* External data memory read strobe */
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220 |
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221 | /*------------------------------------------------
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222 | IP (0xB8) Bit Registers
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223 | ------------------------------------------------*/
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224 | sbit PX0 = 0xB8; /* External Interrupt 0 Priority Bit */
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225 | sbit PT0 = 0xB9; /* Timer 0 Interrupt Priority Bit */
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226 | sbit PX1 = 0xBA; /* External Interrupt 1 Priority Bit */
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227 | sbit PT1 = 0xBB; /* Timer 1 Interrupt Priority Bit */
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228 | sbit PS = 0xBC; /* Serial Port Interrupt Priority Bit */
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229 | sbit PT2 = 0xBD; /* Timer 2 Interrupt Priority Bit */
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230 |
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231 | /*------------------------------------------------
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232 | T2CON (0xC8) Bit Registers
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233 | ------------------------------------------------*/
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234 | sbit CP_RL2= 0xC8; /* 0=Reload, 1=Capture select */
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235 | sbit C_T2 = 0xC9; /* 0=Timer, 1=Counter */
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236 | sbit TR2 = 0xCA; /* 0=Stop timer, 1=Start timer */
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237 | sbit EXEN2= 0xCB; /* Timer 2 external enable */
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238 | sbit TCLK = 0xCC; /* 0=Serial clock uses Timer 1 overflow, 1=Timer 2 */
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239 | sbit RCLK = 0xCD; /* 0=Serial clock uses Timer 1 overflow, 1=Timer 2 */
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240 | sbit EXF2 = 0xCE; /* Timer 2 external flag */
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241 | sbit TF2 = 0xCF; /* Timer 2 overflow flag */
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242 |
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243 | /*------------------------------------------------
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244 | T2MOD (0xC9) Bit Values
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245 | ------------------------------------------------*/
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246 | #define DCEN_ 0x01 /* 1=Timer 2 can be configured as up/down counter */
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247 | #define T2OE_ 0x02 /* Timer 2 output enable */
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248 |
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249 | /*------------------------------------------------
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250 | PSW (0xD0) Bit Registers
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251 | ------------------------------------------------*/
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252 | sbit P = 0xD0; /* Parity Flag */
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253 | sbit FL = 0xD1; /* User Flag */
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254 | sbit OV = 0xD2; /* Overflow Flag */
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255 | sbit RS0 = 0xD3; /* Register Bank Select Bit 0 */
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256 | sbit RS1 = 0xD4; /* Register Bank Select Bit 1 */
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257 | sbit F0 = 0xD5; /* User Flag 0 */
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258 | sbit AC = 0xD6; /* Auxiliary Carry Flag */
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259 | sbit CY = 0xD7; /* Carry Flag */
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260 |
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261 | /*------------------------------------------------
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262 | SPCR (0xD5) Bit Values - Reset Value = 0000.01XX
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263 | ------------------------------------------------*/
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264 | #define SPR0_ 0x01 /* SPI Clock Rate Select bit 0 */
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265 | #define SPR1_ 0x02 /* SPI Clock Rate Select bit 1 */
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266 | /* 00 = Fosc / 4 */
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267 | /* 01 = Fosc / 16 */
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268 | /* 10 = Fosc / 64 */
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269 | /* 11 = Fosc / 128 */
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270 |
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271 | #define CPHA_ 0x04 /* SPI Clock Phase */
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272 | #define CPOL_ 0x08 /* SPI Clock Polarity */
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273 | #define MSTR_ 0x10 /* SPI Master/Slave Select: 0=Slave, 1=Master */
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274 | #define DORD_ 0x20 /* SPI Data Order: 0=MSB First, 1=LSB First */
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275 | #define SPE_ 0x40 /* SPI Enable: 0=Disabled, 1=Enabled */
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276 | #define SPIE_ 0x80 /* SPI Interrupt Enable: 0=Disabled, 1=Enabled */
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277 |
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278 | /*------------------------------------------------
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279 | Interrupt Vectors:
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280 | Interrupt Address = (Number * 8) + 3
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281 | ------------------------------------------------*/
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282 | #define IE0_VECTOR 0 /* 0x03 External Interrupt 0 */
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283 | #define TF0_VECTOR 1 /* 0x0B Timer 0 */
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284 | #define IE1_VECTOR 2 /* 0x13 External Interrupt 1 */
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285 | #define TF1_VECTOR 3 /* 0x1B Timer 1 */
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286 | #define SIO_VECTOR 4 /* 0x23 Serial port */
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287 |
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288 | #define TF2_VECTOR 5 /* 0x2B Timer 2 */
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289 | #define EX2_VECTOR 5 /* 0x2B External Interrupt 2 */
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290 |
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291 | /*------------------------------------------------
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292 | ------------------------------------------------*/
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293 | #endif
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