system_stm32f4xx.c


1
/**

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  ******************************************************************************

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  * @file    system_stm32f4xx.c

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  * @author  MCD Application Team

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  * @version V1.2.0RC2

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  * @date    20-February-2013

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  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.

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  *          This file contains the system clock configuration for STM32F4xx devices,

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  *          and is generated by the clock configuration tool

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  *          stm32f4xx_Clock_Configuration_V1.1.0.xls

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  *

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  * 1.  This file provides two functions and one global variable to be called from

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  *     user application:

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  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier

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  *                      and Divider factors, AHB/APBx prescalers and Flash settings),

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  *                      depending on the configuration made in the clock xls tool.

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  *                      This function is called at startup just after reset and

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  *                      before branch to main program. This call is made inside

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  *                      the "startup_stm32f4xx.s" file.

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  *

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  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used

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  *                                  by the user application to setup the SysTick

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  *                                  timer or configure other parameters.

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  *

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  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must

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  *                                 be called whenever the core clock is changed

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  *                                 during program execution.

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  *

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  * 2. After each device reset the HSI (16 MHz) is used as system clock source.

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  *    Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to

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  *    configure the system clock before to branch to main program.

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  *

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  * 3. If the system clock source selected by user fails to startup, the SystemInit()

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  *    function will do nothing and HSI still used as system clock source. User can

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  *    add some code to deal with this issue inside the SetSysClock() function.

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  *

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  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define

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  *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or

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  *    through PLL, and you are using different crystal you have to adapt the HSE

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  *    value to your own configuration.

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  *

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  * 5. This file configures the system clock as follows:

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  *=============================================================================

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  *=============================================================================

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  *        Supported STM32F40xx/41xx/427x/437x/429x/439x devices

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  *-----------------------------------------------------------------------------

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  *        System Clock source                    | PLL (HSE)

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  *-----------------------------------------------------------------------------

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  *        SYSCLK(Hz)                             | 168000000

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  *-----------------------------------------------------------------------------

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  *        HCLK(Hz)                               | 168000000

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  *-----------------------------------------------------------------------------

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  *        AHB Prescaler                          | 1

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  *-----------------------------------------------------------------------------

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  *        APB1 Prescaler                         | 4

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  *-----------------------------------------------------------------------------

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  *        APB2 Prescaler                         | 2

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  *-----------------------------------------------------------------------------

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  *        HSE Frequency(Hz)                      | 25000000

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  *-----------------------------------------------------------------------------

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  *        PLL_M                                  | 25

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  *-----------------------------------------------------------------------------

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  *        PLL_N                                  | 336

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  *-----------------------------------------------------------------------------

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  *        PLL_P                                  | 2

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  *-----------------------------------------------------------------------------

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  *        PLL_Q                                  | 7

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  *-----------------------------------------------------------------------------

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  *        PLLI2S_N                               | NA

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  *-----------------------------------------------------------------------------

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  *        PLLI2S_R                               | NA

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  *-----------------------------------------------------------------------------

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  *        I2S input clock                        | NA

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  *-----------------------------------------------------------------------------

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  *        VDD(V)                                 | 3.3

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  *-----------------------------------------------------------------------------

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  *        Main regulator output voltage          | Scale1 mode

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  *-----------------------------------------------------------------------------

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  *        Flash Latency(WS)                      | 5

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  *-----------------------------------------------------------------------------

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  *        Prefetch Buffer                        | ON

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  *-----------------------------------------------------------------------------

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  *        Instruction cache                      | ON

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  *-----------------------------------------------------------------------------

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  *        Data cache                             | ON

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  *-----------------------------------------------------------------------------

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  *        Require 48MHz for USB OTG FS,          | Disabled

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  *        SDIO and RNG clock                     |

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  *-----------------------------------------------------------------------------

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  *=============================================================================

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  ******************************************************************************

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  * @attention

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  *

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  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>

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  *

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  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");

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  * You may not use this file except in compliance with the License.

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  * You may obtain a copy of the License at:

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  *

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  *        http://www.st.com/software_license_agreement_liberty_v2

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  *

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  * Unless required by applicable law or agreed to in writing, software

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  * distributed under the License is distributed on an "AS IS" BASIS,

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  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

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  * See the License for the specific language governing permissions and

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  * limitations under the License.

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  *

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  ******************************************************************************

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  */

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/** @addtogroup CMSIS

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  * @{

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  */

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/** @addtogroup stm32f4xx_system

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  * @{

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  */

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/** @addtogroup STM32F4xx_System_Private_Includes

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  * @{

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  */

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#include "stm32f4xx.h"

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/**

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  * @}

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  */

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/** @addtogroup STM32F4xx_System_Private_TypesDefinitions

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  * @{

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  */

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/**

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  * @}

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  */

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/** @addtogroup STM32F4xx_System_Private_Defines

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  * @{

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  */

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/************************* Miscellaneous Configuration ************************/

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/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted

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     on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory  */

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/* #define DATA_IN_ExtSRAM */

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/* #define DATA_IN_ExtSDRAM */

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/*!< Uncomment the following line if you need to relocate your vector Table in

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     Internal SRAM. */

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/* #define VECT_TAB_SRAM */

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#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.

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This value must be a multiple of 0x200. */

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/******************************************************************************/

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/************************* PLL Parameters *************************************/

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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */

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#define PLL_M      25

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#define PLL_N      336

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/* SYSCLK = PLL_VCO / PLL_P */

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#define PLL_P      2

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/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */

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#define PLL_Q      7

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165
/******************************************************************************/

166
167
/**

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  * @}

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  */

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/** @addtogroup STM32F4xx_System_Private_Macros

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  * @{

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  */

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/**

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  * @}

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  */

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/** @addtogroup STM32F4xx_System_Private_Variables

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  * @{

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  */

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uint32_t SystemCoreClock = 168000000;

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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};

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/**

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  * @}

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  */

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/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes

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  * @{

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  */

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static void SetSysClock(void);

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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)

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static void SystemInit_ExtMemCtl(void);

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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */

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/**

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  * @}

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  */

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/** @addtogroup STM32F4xx_System_Private_Functions

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  * @{

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  */

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/**

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  * @brief  Setup the microcontroller system

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  *         Initialize the Embedded Flash Interface, the PLL and update the

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  *         SystemFrequency variable.

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  * @param  None

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  * @retval None

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  */

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void SystemInit(void)

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{

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    /* FPU settings ------------------------------------------------------------*/

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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

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    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */

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#endif

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    /* Reset the RCC clock configuration to the default reset state ------------*/

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    /* Set HSION bit */

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    RCC->CR |= (uint32_t)0x00000001;

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    /* Reset CFGR register */

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    RCC->CFGR = 0x00000000;

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    /* Reset HSEON, CSSON and PLLON bits */

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    RCC->CR &= (uint32_t)0xFEF6FFFF;

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    /* Reset PLLCFGR register */

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    RCC->PLLCFGR = 0x24003010;

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    /* Reset HSEBYP bit */

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    RCC->CR &= (uint32_t)0xFFFBFFFF;

236
237
    /* Disable all interrupts */

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    RCC->CIR = 0x00000000;

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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)

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    SystemInit_ExtMemCtl();

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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */

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    /* Configure the System clock source, PLL Multiplier and Divider factors,

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       AHB/APBx prescalers and Flash settings ----------------------------------*/

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    SetSysClock();

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    /* Configure the Vector Table location add offset address ------------------*/

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#ifdef VECT_TAB_SRAM

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    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */

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#else

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    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */

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#endif

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}

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/**

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   * @brief  Update SystemCoreClock variable according to Clock Register Values.

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  *         The SystemCoreClock variable contains the core clock (HCLK), it can

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  *         be used by the user application to setup the SysTick timer or configure

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  *         other parameters.

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  *

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  * @note   Each time the core clock (HCLK) changes, this function must be called

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  *         to update SystemCoreClock variable value. Otherwise, any configuration

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  *         based on this variable will be incorrect.

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  *

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  * @note   - The system frequency computed by this function is not the real

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  *           frequency in the chip. It is calculated based on the predefined

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  *           constant and the selected clock source:

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  *

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  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)

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  *

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  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)

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  *

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  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)

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  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.

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  *

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  *         (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value

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  *             16 MHz) but the real value may vary depending on the variations

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  *             in voltage and temperature.

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  *

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  *         (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value

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  *              25 MHz), user has to ensure that HSE_VALUE is same as the real

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  *              frequency of the crystal used. Otherwise, this function may

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  *              have wrong result.

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  *

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  *         - The result of this function could be not correct when using fractional

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  *           value for HSE crystal.

288
  *

289
  * @param  None

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  * @retval None

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  */

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void SystemCoreClockUpdate(void)

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{

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    uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;

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    /* Get SYSCLK source -------------------------------------------------------*/

297
    tmp = RCC->CFGR & RCC_CFGR_SWS;

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    switch (tmp)

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    {

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    case 0x00:  /* HSI used as system clock source */

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        SystemCoreClock = HSI_VALUE;

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        break;

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    case 0x04:  /* HSE used as system clock source */

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        SystemCoreClock = HSE_VALUE;

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        break;

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    case 0x08:  /* PLL used as system clock source */

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309
        /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N

310
           SYSCLK = PLL_VCO / PLL_P

311
           */

312
        pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;

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        pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;

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315
        if (pllsource != 0)

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        {

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            /* HSE used as PLL clock source */

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            pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);

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        }

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        else

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        {

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            /* HSI used as PLL clock source */

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            pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);

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        }

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326
        pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;

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        SystemCoreClock = pllvco/pllp;

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        break;

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    default:

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        SystemCoreClock = HSI_VALUE;

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        break;

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    }

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    /* Compute HCLK frequency --------------------------------------------------*/

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    /* Get HCLK prescaler */

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    tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];

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    /* HCLK frequency */

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    SystemCoreClock >>= tmp;

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}

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340
/**

341
  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,

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  *         AHB/APBx prescalers and Flash settings

343
  * @Note   This function should be called only once the RCC clock configuration

344
  *         is reset to the default reset state (done in SystemInit() function).

345
  * @param  None

346
  * @retval None

347
  */

348
static void SetSysClock(void)

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{

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    /******************************************************************************/

351
    /*            PLL (clocked by HSE) used as System clock source                */

352
    /******************************************************************************/

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    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

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    /* Enable HSE */

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    RCC->CR |= ((uint32_t)RCC_CR_HSEON);

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358
    /* Wait till HSE is ready and if Time out is reached exit */

359
    do

360
    {

361
        HSEStatus = RCC->CR & RCC_CR_HSERDY;

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        StartUpCounter++;

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    }

364
    while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

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366
    if ((RCC->CR & RCC_CR_HSERDY) != RESET)

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    {

368
        HSEStatus = (uint32_t)0x01;

369
    }

370
    else

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    {

372
        HSEStatus = (uint32_t)0x00;

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    }

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375
    if (HSEStatus == (uint32_t)0x01)

376
    {

377
        /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */

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        RCC->APB1ENR |= RCC_APB1ENR_PWREN;

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        PWR->CR |= PWR_CR_VOS;

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        /* HCLK = SYSCLK / 1*/

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        RCC->CFGR |= RCC_CFGR_HPRE_DIV1;

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384
        /* PCLK2 = HCLK / 2*/

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        RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;

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        /* PCLK1 = HCLK / 4*/

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        RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;

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        /* Configure the main PLL */

391
        RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |

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                       (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);

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        /* Enable the main PLL */

395
        RCC->CR |= RCC_CR_PLLON;

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        /* Wait till the main PLL is ready */

398
        while((RCC->CR & RCC_CR_PLLRDY) == 0)

399
        {

400
        }

401
402
        /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

403
        FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;

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405
        /* Select the main PLL as system clock source */

406
        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

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        RCC->CFGR |= RCC_CFGR_SW_PLL;

408
409
        /* Wait till the main PLL is used as system clock source */

410
        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);

411
        {

412
        }

413
    }

414
    else

415
    {

416
        /* If HSE fails to start-up, the application will have wrong clock

417
             configuration. User can add here some code to deal with this error */

418
    }

419
420
}

421
422
/**

423
  * @brief  Setup the external memory controller. Called in startup_stm32f4xx.s

424
  *          before jump to __main

425
  * @param  None

426
  * @retval None

427
  */

428
#ifdef DATA_IN_ExtSRAM

429
/**

430
  * @brief  Setup the external memory controller.

431
  *         Called in startup_stm32f4xx.s before jump to main.

432
  *         This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards

433
  *         This SRAM will be used as program data memory (including heap and stack).

434
  * @param  None

435
  * @retval None

436
  */

437
void SystemInit_ExtMemCtl(void)

438
{

439
    /*-- GPIOs Configuration -----------------------------------------------------*/

440
    /*

441
     +-------------------+--------------------+------------------+--------------+

442
     +                       SRAM pins assignment                               +

443
     +-------------------+--------------------+------------------+--------------+

444
     | PD0  <-> FMC_D2  | PE0  <-> FMC_NBL0 | PF0  <-> FMC_A0 | PG0 <-> FMC_A10 |

445
     | PD1  <-> FMC_D3  | PE1  <-> FMC_NBL1 | PF1  <-> FMC_A1 | PG1 <-> FMC_A11 |

446
     | PD4  <-> FMC_NOE | PE3  <-> FMC_A19  | PF2  <-> FMC_A2 | PG2 <-> FMC_A12 |

447
     | PD5  <-> FMC_NWE | PE4  <-> FMC_A20  | PF3  <-> FMC_A3 | PG3 <-> FMC_A13 |

448
     | PD8  <-> FMC_D13 | PE7  <-> FMC_D4   | PF4  <-> FMC_A4 | PG4 <-> FMC_A14 |

449
     | PD9  <-> FMC_D14 | PE8  <-> FMC_D5   | PF5  <-> FMC_A5 | PG5 <-> FMC_A15 |

450
     | PD10 <-> FMC_D15 | PE9  <-> FMC_D6   | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |

451
     | PD11 <-> FMC_A16 | PE10 <-> FMC_D7   | PF13 <-> FMC_A7 |-----------------+

452
     | PD12 <-> FMC_A17 | PE11 <-> FMC_D8   | PF14 <-> FMC_A8 |

453
     | PD13 <-> FMC_A18 | PE12 <-> FMC_D9   | PF15 <-> FMC_A9 |

454
     | PD14 <-> FMC_D0  | PE13 <-> FMC_D10  |-----------------+

455
     | PD15 <-> FMC_D1  | PE14 <-> FMC_D11  |

456
     |                  | PE15 <-> FMC_D12  |

457
     +------------------+------------------+

458
    */

459
    /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */

460
    RCC->AHB1ENR   |= 0x00000078;

461
462
    /* Connect PDx pins to FMC Alternate function */

463
    GPIOD->AFR[0]  = 0x00cc00cc;

464
    GPIOD->AFR[1]  = 0xcccccccc;

465
    /* Configure PDx pins in Alternate function mode */

466
    GPIOD->MODER   = 0xaaaa0a0a;

467
    /* Configure PDx pins speed to 100 MHz */

468
    GPIOD->OSPEEDR = 0xffff0f0f;

469
    /* Configure PDx pins Output type to push-pull */

470
    GPIOD->OTYPER  = 0x00000000;

471
    /* No pull-up, pull-down for PDx pins */

472
    GPIOD->PUPDR   = 0x00000000;

473
474
    /* Connect PEx pins to FMC Alternate function */

475
    GPIOE->AFR[0]  = 0xcccccccc;

476
    GPIOE->AFR[1]  = 0xcccccccc;

477
    /* Configure PEx pins in Alternate function mode */

478
    GPIOE->MODER   = 0xaaaaaaaa;

479
    /* Configure PEx pins speed to 100 MHz */

480
    GPIOE->OSPEEDR = 0xffffffff;

481
    /* Configure PEx pins Output type to push-pull */

482
    GPIOE->OTYPER  = 0x00000000;

483
    /* No pull-up, pull-down for PEx pins */

484
    GPIOE->PUPDR   = 0x00000000;

485
486
    /* Connect PFx pins to FMC Alternate function */

487
    GPIOF->AFR[0]  = 0x00cccccc;

488
    GPIOF->AFR[1]  = 0xcccc0000;

489
    /* Configure PFx pins in Alternate function mode */

490
    GPIOF->MODER   = 0xaa000aaa;

491
    /* Configure PFx pins speed to 100 MHz */

492
    GPIOF->OSPEEDR = 0xff000fff;

493
    /* Configure PFx pins Output type to push-pull */

494
    GPIOF->OTYPER  = 0x00000000;

495
    /* No pull-up, pull-down for PFx pins */

496
    GPIOF->PUPDR   = 0x00000000;

497
498
    /* Connect PGx pins to FMC Alternate function */

499
    GPIOG->AFR[0]  = 0x00cccccc;

500
    GPIOG->AFR[1]  = 0x000000c0;

501
    /* Configure PGx pins in Alternate function mode */

502
    GPIOG->MODER   = 0x00080aaa;

503
    /* Configure PGx pins speed to 100 MHz */

504
    GPIOG->OSPEEDR = 0x000c0fff;

505
    /* Configure PGx pins Output type to push-pull */

506
    GPIOG->OTYPER  = 0x00000000;

507
    /* No pull-up, pull-down for PGx pins */

508
    GPIOG->PUPDR   = 0x00000000;

509
510
    /*-- FMC Configuration ------------------------------------------------------*/

511
    /* Enable the FMC interface clock */

512
    RCC->AHB3ENR         |= 0x00000001;

513
514
    /* Configure and enable Bank1_SRAM2 */

515
    FMC_Bank1->BTCR[2]  = 0x00001011;

516
    FMC_Bank1->BTCR[3]  = 0x00000201;

517
    FMC_Bank1E->BWTR[2] = 0x0fffffff;

518
    /*

519
      Bank1_SRAM2 is configured as follow:

520
521
      NORSRAMTimingStructure.FMC_AddressSetupTime = 1;

522
      NORSRAMTimingStructure.FMC_AddressHoldTime = 0;

523
      NORSRAMTimingStructure.FMC_DataSetupTime = 2;

524
      NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;

525
      NORSRAMTimingStructure.FMC_CLKDivision = 0;

526
      NORSRAMTimingStructure.FMC_DataLatency = 0;

527
      NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;

528
529
      FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;

530
      FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;

531
      FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;

532
      FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;

533
      FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;

534
      FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;

535
      FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;

536
      FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;

537
      FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;

538
      FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;

539
      FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;

540
      FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;

541
      FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;

542
      FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;

543
      FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;

544
      FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;

545
    */

546
547
}

548
#endif /* DATA_IN_ExtSRAM */

549
550
#ifdef DATA_IN_ExtSDRAM

551
/**

552
  * @brief  Setup the external memory controller.

553
  *         Called in startup_stm32f4xx.s before jump to main.

554
  *         This function configures the external SDRAM mounted on STM324x9I_EVAL board

555
  *         This SDRAM will be used as program data memory (including heap and stack).

556
  * @param  None

557
  * @retval None

558
  */

559
void SystemInit_ExtMemCtl(void)

560
{

561
    register uint32_t tmpreg = 0, timeout = 0xFFFF;

562
    register uint32_t index;

563
564
    /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface

565
        clock */

566
    RCC->AHB1ENR |= 0x000001FC;

567
568
    /* Connect PCx pins to FMC Alternate function */

569
    GPIOC->AFR[0]  = 0x0000000c;

570
    GPIOC->AFR[1]  = 0x00007700;

571
    /* Configure PCx pins in Alternate function mode */

572
    GPIOC->MODER   = 0x00a00002;

573
    /* Configure PCx pins speed to 50 MHz */

574
    GPIOC->OSPEEDR = 0x00a00002;

575
    /* Configure PCx pins Output type to push-pull */

576
    GPIOC->OTYPER  = 0x00000000;

577
    /* No pull-up, pull-down for PCx pins */

578
    GPIOC->PUPDR   = 0x00500000;

579
580
    /* Connect PDx pins to FMC Alternate function */

581
    GPIOD->AFR[0]  = 0x000000CC;

582
    GPIOD->AFR[1]  = 0xCC000CCC;

583
    /* Configure PDx pins in Alternate function mode */

584
    GPIOD->MODER   = 0xA02A000A;

585
    /* Configure PDx pins speed to 50 MHz */

586
    GPIOD->OSPEEDR = 0xA02A000A;

587
    /* Configure PDx pins Output type to push-pull */

588
    GPIOD->OTYPER  = 0x00000000;

589
    /* No pull-up, pull-down for PDx pins */

590
    GPIOD->PUPDR   = 0x00000000;

591
592
    /* Connect PEx pins to FMC Alternate function */

593
    GPIOE->AFR[0]  = 0xC00000CC;

594
    GPIOE->AFR[1]  = 0xCCCCCCCC;

595
    /* Configure PEx pins in Alternate function mode */

596
    GPIOE->MODER   = 0xAAAA800A;

597
    /* Configure PEx pins speed to 50 MHz */

598
    GPIOE->OSPEEDR = 0xAAAA800A;

599
    /* Configure PEx pins Output type to push-pull */

600
    GPIOE->OTYPER  = 0x00000000;

601
    /* No pull-up, pull-down for PEx pins */

602
    GPIOE->PUPDR   = 0x00000000;

603
604
    /* Connect PFx pins to FMC Alternate function */

605
    GPIOF->AFR[0]  = 0xcccccccc;

606
    GPIOF->AFR[1]  = 0xcccccccc;

607
    /* Configure PFx pins in Alternate function mode */

608
    GPIOF->MODER   = 0xAA800AAA;

609
    /* Configure PFx pins speed to 50 MHz */

610
    GPIOF->OSPEEDR = 0xAA800AAA;

611
    /* Configure PFx pins Output type to push-pull */

612
    GPIOF->OTYPER  = 0x00000000;

613
    /* No pull-up, pull-down for PFx pins */

614
    GPIOF->PUPDR   = 0x00000000;

615
616
    /* Connect PGx pins to FMC Alternate function */

617
    GPIOG->AFR[0]  = 0xcccccccc;

618
    GPIOG->AFR[1]  = 0xcccccccc;

619
    /* Configure PGx pins in Alternate function mode */

620
    GPIOG->MODER   = 0xaaaaaaaa;

621
    /* Configure PGx pins speed to 50 MHz */

622
    GPIOG->OSPEEDR = 0xaaaaaaaa;

623
    /* Configure PGx pins Output type to push-pull */

624
    GPIOG->OTYPER  = 0x00000000;

625
    /* No pull-up, pull-down for PGx pins */

626
    GPIOG->PUPDR   = 0x00000000;

627
628
    /* Connect PHx pins to FMC Alternate function */

629
    GPIOH->AFR[0]  = 0x00C0CC00;

630
    GPIOH->AFR[1]  = 0xCCCCCCCC;

631
    /* Configure PHx pins in Alternate function mode */

632
    GPIOH->MODER   = 0xAAAA08A0;

633
    /* Configure PHx pins speed to 50 MHz */

634
    GPIOH->OSPEEDR = 0xAAAA08A0;

635
    /* Configure PHx pins Output type to push-pull */

636
    GPIOH->OTYPER  = 0x00000000;

637
    /* No pull-up, pull-down for PHx pins */

638
    GPIOH->PUPDR   = 0x00000000;

639
640
    /* Connect PIx pins to FMC Alternate function */

641
    GPIOI->AFR[0]  = 0xCCCCCCCC;

642
    GPIOI->AFR[1]  = 0x00000CC0;

643
    /* Configure PIx pins in Alternate function mode */

644
    GPIOI->MODER   = 0x0028AAAA;

645
    /* Configure PIx pins speed to 50 MHz */

646
    GPIOI->OSPEEDR = 0x0028AAAA;

647
    /* Configure PIx pins Output type to push-pull */

648
    GPIOI->OTYPER  = 0x00000000;

649
    /* No pull-up, pull-down for PIx pins */

650
    GPIOI->PUPDR   = 0x00000000;

651
652
    /*-- FMC Configuration ------------------------------------------------------*/

653
    /* Enable the FMC interface clock */

654
    RCC->AHB3ENR |= 0x00000001;

655
656
    /* Configure and enable SDRAM bank1 */

657
    FMC_Bank5_6->SDCR[0] = 0x000029D0;

658
    FMC_Bank5_6->SDTR[0] = 0x01115351;

659
660
    /* SDRAM initialization sequence */

661
    /* Clock enable command */

662
    FMC_Bank5_6->SDCMR = 0x00000011;

663
    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;

664
    while((tmpreg != 0) & (timeout-- > 0))

665
    {

666
        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;

667
    }

668
669
    /* Delay */

670
    for (index = 0; index<1000; index++);

671
672
    /* PALL command */

673
    FMC_Bank5_6->SDCMR = 0x00000012;

674
    timeout = 0xFFFF;

675
    while((tmpreg != 0) & (timeout-- > 0))

676
    {

677
        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;

678
    }

679
680
    /* Auto refresh command */

681
    FMC_Bank5_6->SDCMR = 0x00000073;

682
    timeout = 0xFFFF;

683
    while((tmpreg != 0) & (timeout-- > 0))

684
    {

685
        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;

686
    }

687
688
    /* MRD register program */

689
    FMC_Bank5_6->SDCMR = 0x00046014;

690
    timeout = 0xFFFF;

691
    while((tmpreg != 0) & (timeout-- > 0))

692
    {

693
        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;

694
    }

695
696
    /* Set refresh count */

697
    tmpreg = FMC_Bank5_6->SDRTR;

698
    FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));

699
700
    /* Disable write protection */

701
    tmpreg = FMC_Bank5_6->SDCR[0];

702
    FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);

703
704
    /*

705
      Bank1_SDRAM is configured as follow:

706
707
      FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;

708
      FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;

709
      FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;

710
      FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;

711
      FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;

712
      FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;

713
      FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;

714
715
      FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;

716
      FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;

717
      FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;

718
      FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;

719
      FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;

720
      FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;

721
      FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;

722
      FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;

723
      FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;

724
      FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;

725
      FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;

726
    */

727
728
}

729
#endif /* DATA_IN_ExtSDRAM */

730
731
732
/**

733
  * @}

734
  */

735
736
/**

737
  * @}

738
  */

739
740
/**

741
  * @}

742
  */

743
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/