can_controller.vhd

library ieee;
use ieee.std_logic_1164.all;
entity can_controller is
  --- can ctrl input ---
  clk      : in std_logic; -- clock
  reset    : in std_logic; -- low active reset
  can_data : inout std_logic_vector(88 downto 0); -- CAN_DATA := FRAME INFO(8)+ ID(16)+ DATA(64)
  can_rd  : in std_logic; -- read can message
  can_wr  : in std_logic; -- write can message
  --- can ctrl output ---
  -- interface for can_top enity
  rst   : out std_logic; -- reset
  ale   : out std_logic; -- adress letch enable
  rd     : out std_logic; -- read 8 bit
  wr     : out std_logic; -- write 8 bit 
  cs_can : out std_logic; -- chip select
  port_0 : inout std_logic_vector(7 downto 0) -- data buffer
end can_controller;
architecture beh_can_controller of can_controller is
type type_main_state is (IDLE,
                 CONFIGURE,
                 TRANSMIT,
                 RECEIVE);
type type_config_state is (RESET_MODE_ON,
                  ACTIVE_BASIC_CONFIG,
                  SET_BAUD_SYNC,
                  SET_ACCEPTANCE_MASK,
                  SET_ACCEPTANCE_MASK2,
                  SET_BUS_TIMING,
                  RESET_MODE_OFF);
type type_reg_read_state is ( RD_SET_CS,
                  RD_SET_REG_ADR,
                  RD_GET_reg_data_buffer);
type type_can_read_state is ( FRAME_INFORMATION_RD,
                    IDENTIFIER_0_RD,
                    IDENTIFIER_1_RD,
                    BYTE_0_RD,
                     BYTE_1_RD,
                    BYTE_2_RD,
                    BYTE_3_RD,
                    BYTE_4_RD,
                    BYTE_5_RD,
                    BYTE_6_RD,
                    BYTE_7_RD);
type type_can_write_state is ( FRAME_INFORMATION_WR,
                     IDENTIFIER_0_WR,
                     IDENTIFIER_1_WR,
                     BYTE_0_WR,
                      BYTE_1_WR,
                     BYTE_2_WR,
                     BYTE_3_WR,
                     BYTE_4_WR,
                     BYTE_5_WR,
                     BYTE_6_WR,
                     BYTE_7_WR);  
-- STATE HANDLER --                                  
signal state_main : type_main_state := IDLE;
signal state_config : type_config_state := RESET_MODE_ON;
signal state_can_rd : type_can_read_state := FRAME_INFORMATION_RD;
signal state_can_wr : type_can_write_state := FRAME_INFORMATION_WR;
-- CAN READY FLAGS --
shared variable ready_can_cfg : boolean := false;
shared variable ready_can_wr : boolean := false;
shared variable ready_can_rd : boolean := false;
-- REG READY FLAGS --
signal ready_reg_wr : boolean := false;
signal ready_reg_rd : boolean := false;
-- TEMP VARIABLES --
shared variable reg_data_buffer : std_logic_vector(7 downto 0); 
-- PROCEDURES
procedure CAN_REG_READ ( ADDRESS : in std_logic_vector(7 downto 0);
                 DATA : out std_logic_vector(7 downto 0);
                 signal READY_FLAG : out boolean ) is
  cs_can <= '1';
  ale <= '1';
  port_0 <= ADDRESS; -- PORT_0 RELEVENT FOR RACE CONDITION
  ale <= '0';
  rd <= '1';
  DATA := port_0; 
  rd <= '0';
  cs_can <= '0';
  READY_FLAG <= true;
end procedure CAN_REG_READ;
procedure CAN_REG_WRITE( ADDRESS : in std_logic_vector(7 downto 0);
                 DATA : in std_logic_vector(7 downto 0);
                 signal READY_FLAG : out boolean ) is
  cs_can <= '1';
  ale <= '1';
  port_0 <= ADDRESS;
  ale <= '0';
  wr <= '1';
  port_0 <= DATA;
  wr <= '0';
  cs_can <= '0';
end procedure CAN_REG_WRITE;
  process(clk,reset) -- MAIN STATEMACHINE
  begin
    if reset = '0' then -- aktive low
      state_main <= CONFIGURE;
    elsif rising_edge(clk) and ready_can_cfg then
      if can_rd = '1' then
        state_main <= RECEIVE;
      elsif can_wr = '1' then
        state_main <= TRANSMIT;
      end if;
    end if;
  end process;
  config : process(clk) -- CONFIGURE STATEMACHINE
  begin
    if state_main = CONFIGURE then
      case state_config is
        when RESET_MODE_ON =>
          ready_can_cfg := false;
          CAN_REG_WRITE(x"00",x"01",ready_reg_wr);
          if ready_reg_wr = true then
            ready_reg_wr <= false;
            state_config <= ACTIVE_BASIC_CONFIG;
          end if;
        when ACTIVE_BASIC_CONFIG =>
          --CAN_REG_WRITE(x"1F",x"07",ready_reg_wr);
          if ready_reg_wr = true then
            ready_reg_wr <= false;
            state_config <= SET_BAUD_SYNC;
          end if;
        when SET_BAUD_SYNC =>
          --CAN_REG_WRITE(x"06",x"01",ready_reg_wr);
          if ready_reg_wr = true then
            ready_reg_wr <= false;
            state_config <= SET_ACCEPTANCE_MASK;
          end if;
        when SET_ACCEPTANCE_MASK =>
          --CAN_REG_WRITE(x"04",x"00",ready_reg_wr);          
          if ready_reg_wr = true then
            ready_reg_wr <= false;
            state_config <= SET_ACCEPTANCE_MASK2;
          end if;
        when SET_ACCEPTANCE_MASK2 =>
          --CAN_REG_WRITE(x"05",x"00",ready_reg_wr);          
          if ready_reg_wr = true then
            ready_reg_wr <= false;
            state_config <= SET_BUS_TIMING;
          end if;      
        when SET_BUS_TIMING =>
          --CAN_REG_WRITE(x"07",x"7F",ready_reg_wr);          
          if ready_reg_wr = true then
            ready_reg_wr <= false;
            state_config <= RESET_MODE_OFF;
          end if;
        when RESET_MODE_OFF =>
          --CAN_REG_WRITE(x"00",x"00",ready_reg_wr);          
          if ready_reg_wr = true then
            ready_reg_wr <= false;
            state_config <= RESET_MODE_ON;
          end if;
          ready_can_cfg := true;
      end case;
    end if;
  end process config;
  can_read : process(clk) -- CAN READ STATEMACHINE -> READS 88Bit
  begin
    if state_main = RECEIVE then
      case state_can_rd is
        when FRAME_INFORMATION_RD =>
          ready_can_rd := false;
          CAN_REG_READ(x"10", reg_data_buffer, ready_reg_rd);
          if ready_reg_rd then
            can_data(7 downto 0) <= reg_data_buffer(7 downto 0);
            ready_reg_rd <= false;
            state_can_rd <= IDENTIFIER_0_RD;
          end if;
        when IDENTIFIER_0_RD =>
          CAN_REG_READ(x"11", reg_data_buffer, ready_reg_rd);
          if ready_reg_rd then
            can_data(15 downto 8) <= reg_data_buffer(7 downto 0);
            ready_reg_rd <= false;
            state_can_rd <= IDENTIFIER_1_RD;
          end if;
        when IDENTIFIER_1_RD =>
          CAN_REG_READ(x"12", reg_data_buffer, ready_reg_rd);
          if ready_reg_rd then
            can_data(23 downto 16) <= reg_data_buffer(7 downto 0);
            ready_reg_rd <= false;
            state_can_rd <= BYTE_0_RD;
          end if;
        when BYTE_0_RD =>
          CAN_REG_READ(x"13", reg_data_buffer, ready_reg_rd);
          if ready_reg_rd then
            can_data(31 downto 24) <= reg_data_buffer(7 downto 0);
            ready_reg_rd <= false;
            state_can_rd <= BYTE_1_RD;
          end if;
        when BYTE_1_RD =>
          CAN_REG_READ(x"14", reg_data_buffer, ready_reg_rd);
          if ready_reg_rd then
            can_data(39 downto 32) <= reg_data_buffer(7 downto 0);
            ready_reg_rd <= false;
            state_can_rd <= BYTE_2_RD;
          end if;
        when BYTE_2_RD =>
          CAN_REG_READ(x"15", reg_data_buffer, ready_reg_rd);
          if ready_reg_rd then
            can_data(47 downto 40) <= reg_data_buffer(7 downto 0);
            ready_reg_rd <= false;
            state_can_rd <= BYTE_3_RD;
          end if;
        when BYTE_3_RD =>
          CAN_REG_READ(x"16", reg_data_buffer, ready_reg_rd);
          if ready_reg_rd then
            can_data(55 downto 48) <= reg_data_buffer(7 downto 0);
            ready_reg_rd <= false;
            state_can_rd <= BYTE_4_RD;
          end if;
        when BYTE_4_RD =>
          CAN_REG_READ(x"17", reg_data_buffer, ready_reg_rd);
          if ready_reg_rd then
            can_data(63 downto 56) <= reg_data_buffer(7 downto 0);
            ready_reg_rd <= false;
            state_can_rd <= BYTE_5_RD;
          end if;
        when BYTE_5_RD =>
          CAN_REG_READ(x"18", reg_data_buffer, ready_reg_rd);
          if ready_reg_rd then
            can_data(71 downto 64) <= reg_data_buffer(7 downto 0);
            ready_reg_rd <= false;
            state_can_rd <= BYTE_6_RD;
          end if;
        when BYTE_6_RD =>
          CAN_REG_READ(x"19", reg_data_buffer, ready_reg_rd);
          if ready_reg_rd then
            can_data(79 downto 72) <= reg_data_buffer(7 downto 0);
            ready_reg_rd <= false;
            state_can_rd <= BYTE_7_RD;
          end if;
        when BYTE_7_RD =>
          CAN_REG_READ(x"1A", reg_data_buffer, ready_reg_rd);
          if ready_reg_rd then
            can_data(87 downto 80) <= reg_data_buffer(7 downto 0);
            ready_reg_rd <= false;
            state_can_rd <= FRAME_INFORMATION_RD;
          end if;
          ready_can_rd := true;
      end case;
    end if;
  end process can_read;
--  can_write: process(clk) -- CAN WRITE STATEMACHINE -> WRITE 88Bit
--  begin
--    if state_main = TRANSMIT then
--      case state_can_wr is
--        when FRAME_INFORMATION_WR =>
--          ready_can_wr := false;
--          --CAN_REG_WRITE(x"10", can_data(7 downto 0), ready_reg_wr);
--          if ready_reg_wr = true then
--            ready_reg_wr <= false;
--            state_can_wr <= IDENTIFIER_0_WR;
--          end if;
--        when IDENTIFIER_0_WR =>
--          --CAN_REG_WRITE(x"11", can_data(15 downto 8), ready_reg_wr);
--          if ready_reg_wr = true then
--            ready_reg_wr <= false;
--            state_can_wr <= IDENTIFIER_1_WR;
--          end if;
--        when IDENTIFIER_1_WR =>
--          --CAN_REG_WRITE(x"12", can_data(23 downto 16), ready_reg_wr);
--          if ready_reg_wr = true then
--            ready_reg_wr <= false;
--            state_can_wr <= BYTE_0_WR;
--          end if;
--        when BYTE_0_WR =>
--          --CAN_REG_WRITE(x"13", can_data(31 downto 24), ready_reg_wr);
--          if ready_reg_wr = true then
--            ready_reg_wr <= false;
--            state_can_wr <= BYTE_1_WR;
--          end if;
--        when BYTE_1_WR =>
--          --CAN_REG_WRITE(x"14", can_data(39 downto 32), ready_reg_wr);
--          if ready_reg_wr = true then
--            ready_reg_wr <= false;
--            state_can_wr <= BYTE_2_WR;
--          end if;
--        when BYTE_2_WR =>
--          --CAN_REG_WRITE(x"15", can_data(47 downto 40), ready_reg_wr);
--          if ready_reg_wr = true then
--            ready_reg_wr <= false;
--            state_can_wr <= BYTE_3_WR;
--          end if;
--        when BYTE_3_WR =>
--          --CAN_REG_WRITE(x"16", can_data(55 downto 48), ready_reg_wr);
--          if ready_reg_wr = true then
--            ready_reg_wr <= false;
--            state_can_wr <= BYTE_4_WR;
--          end if;
--        when BYTE_4_WR =>
--          --CAN_REG_WRITE(x"17", can_data(63 downto 56), ready_reg_wr);
--          if ready_reg_wr = true then
--            ready_reg_wr <= false;
--            state_can_wr <= BYTE_5_WR;
--          end if;
--        when BYTE_5_WR =>
--          --CAN_REG_WRITE(x"18", can_data(71 downto 64), ready_reg_wr);
--          if ready_reg_wr = true then
--            ready_reg_wr <= false;
--            state_can_wr <= BYTE_6_WR;
--          end if;
--        when BYTE_6_WR =>
--          --CAN_REG_WRITE(x"19", can_data(79 downto 72), ready_reg_wr);
--          if ready_reg_wr = true then
--            ready_reg_wr <= false;
--            state_can_wr <= BYTE_7_WR;
--          end if;
--        when BYTE_7_WR =>
--          --CAN_REG_WRITE(x"1A", can_data(87 downto 80), ready_reg_wr);
--          if ready_reg_wr = true then
--            ready_reg_wr <= false;
--            state_can_wr <= FRAME_INFORMATION_WR;
--          end if;
--          ready_can_wr := true;
--      end case;
--    end if;
--  end process can_write;
end beh_can_controller;
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