1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.STD_LOGIC_ARITH.ALL;
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4 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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5 | use IEEE.NUMERIC_STD.ALL;
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6 |
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7 | USE work.LCSE.all;
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8 |
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9 | entity ALU is
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10 | Port ( reset : in std_logic;
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11 | clk : in std_logic;
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12 | u_instruction : in alu_op;
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13 | flagZ : out std_logic;
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14 | flagC : out std_logic;
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15 | flagN : out std_logic;
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16 | flagE : out std_logic;
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17 | index_reg : out std_logic_vector (7 downto 0);
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18 | Databus : inout std_logic_vector(7 downto 0));
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19 | end ALU;
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20 |
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21 | architecture Behavioral of ALU is
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22 |
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23 | signal A_reg, B_reg, ACC_reg, A_tmp, B_tmp, ACC_temp, Index_tmp, internal_bus,
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24 | ALU_out: std_logic_vector (7 downto 0);
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25 | signal Flags_tmp : std_logic_vector (3 downto 0);
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26 | signal Out_enable : std_logic;
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27 |
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28 | begin
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29 |
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30 | ALU_OP : process (reset, A_reg, B_reg, ACC_reg, u_instruction, Databus,
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31 | internal_bus)
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32 | begin
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33 |
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34 | ALU_Out <= (others => '0');
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35 | ACC_Temp <= ALU_out;
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36 | A_tmp <= Databus;
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37 | B_tmp <= Databus;
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38 | Flags_tmp <= "0001";
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39 | out_enable <= '0';
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40 | Index_tmp <= ACC_reg;
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41 |
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42 | CASE u_instruction is
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43 |
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44 | when op_lda =>
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45 | A_tmp <= databus;
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46 |
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47 | when op_ldb =>
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48 | B_tmp <= Databus;
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49 |
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50 | when op_add =>
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51 | ALU_out <= (A_reg + B_reg);
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52 | ACC_temp <= ALU_out;
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53 | if (ALU_Out = "00000000") then
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54 | Flags_tmp (0) <= '1'; -- Z = 1
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55 | end if;
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56 | if (( (A_reg(7) OR B_reg(7)) AND (NOT ALU_Out (7))) = '1') then
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57 | Flags_tmp (1) <= '1'; -- C = 1
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58 | end if;
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59 | if (( (A_reg(3) OR B_reg(3)) AND (NOT ALU_Out (3))) = '1') then
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60 | Flags_tmp (2) <= '1'; -- N = 1
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61 | end if;
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62 |
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63 | --------------------------------------------------------------------------
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64 |
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65 | -- Noch mehr uinstrutions
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66 |
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67 | --------------------------------------------------------------------------
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68 |
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69 |
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70 | when others => ALU_Out <= (others => '0');
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71 |
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72 | end CASE;
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73 |
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74 | end process ALU_OP;
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75 |
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76 | process (reset, clk)
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77 | begin
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78 |
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79 | if(reset = '0') then
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80 |
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81 | A_reg <= (others => '0');
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82 | B_reg <= (others => '0');
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83 | ACC_reg <= (others => '0');
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84 | Index_reg <= (others => '0');
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85 | internal_bus <= (others => '0');
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86 | Databus <= (others => 'Z');
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87 |
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88 | elsif (clk'event and clk ='1') then
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89 |
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90 | flagZ <= Flags_tmp (0);
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91 | flagC <= Flags_tmp (1);
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92 | flagN <= Flags_tmp (2);
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93 | flagE <= Flags_tmp (3);
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94 |
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95 | if(out_enable = '1') then
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96 | Databus <= ACC_reg;
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97 | end if;
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98 |
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99 | A_reg <= A_tmp;
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100 | B_reg <= B_tmp;
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101 |
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102 | ACC_reg <= ACC_Temp;
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103 | Index_reg <= Index_tmp;
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104 |
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105 | end if;
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106 |
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107 | end process;
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108 |
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109 | end Behavioral;
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