1 | void board_init ( void )
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2 | {
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3 | RTC_init();
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4 | CLKSYS_Prescalers_Config( CLK_PSADIV_1_gc, CLK_PSBCDIV_1_1_gc ) ;
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5 | Clock_init();
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6 | exClock_init();
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7 | PLL_init();
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8 |
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9 | sei();
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10 | PMIC.CTRL |= PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_HILVLEN_bm;
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11 | PMIC.INTPRI=0x00;
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12 | }
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13 |
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14 | void RTC_init ( void )
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15 | {
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16 | OSC.CTRL |= OSC_RC32KEN_bm ;
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17 | while ( ( OSC.STATUS & OSC_RC32KRDY_bm ) == 0) ;
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18 | CLK.RTCCTRL = CLK_RTCSRC_RCOSC_gc | CLK_RTCEN_bm ;
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19 | }
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20 | void Clock_init ( void )
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21 | {
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22 | //OSC.CTRL |= OSC_RC32MEN_bm;
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23 | //while(!(OSC.STATUS & OSC_RC32MRDY_bm));
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24 | //CCP = CCP_IOREG_gc;
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25 | //CLK.CTRL = CLK_SCLKSEL_RC32M_gc;
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26 |
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27 | // Configure clock to 32MHz
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28 | OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; /* Enable the internal 32MHz & 32KHz oscillators */
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29 | while(!(OSC.STATUS & OSC_RC32KRDY_bm)); /* Wait for 32Khz oscillator to stabilize */
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30 | while(!(OSC.STATUS & OSC_RC32MRDY_bm)); /* Wait for 32MHz oscillator to stabilize */
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31 | DFLLRC32M.CTRL = DFLL_ENABLE_bm ; /* Enable DFLL - defaults to calibrate against internal 32Khz clock */
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32 | CCP = CCP_IOREG_gc; /* Disable register security for clock update */
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33 | CLK.CTRL = CLK_SCLKSEL_RC32M_gc; /* Switch to 32MHz clock */
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34 | OSC.CTRL &= ~OSC_RC2MEN_bm; /* Disable 2Mhz oscillator */
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35 | }
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36 | void exClock_init ( void )
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37 | {
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38 | /*
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39 | OSC_XOSCCTRL = OSC_XOSCSEL_XTAL_16KCLK_gc |
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40 | OSC_FRQRANGE_12TO16_gc;
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41 | OSC.CTRL |= OSC_XOSCEN_bm;
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42 | while(!(OSC.STATUS & OSC_XOSCRDY_bm));
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43 | CCP = CCP_IOREG_gc;
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44 | CLK.CTRL = CLK_SCLKSEL_XOSC_gc;
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45 | */
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46 |
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47 | OSC.XOSCCTRL = OSC_FRQRANGE_12TO16_gc | OSC_XOSCSEL_XTAL_256CLK_gc;
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48 | OSC.CTRL |= OSC_XOSCEN_bm;
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49 | while( (OSC.STATUS & OSC_XOSCRDY_bm) == 0){
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50 | //PORTF.OUTTGL = (1<<6);
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51 | //PORTK.OUTTGL = (1<<0); //toggle led //toggle led
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52 | }
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53 | OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | (2 << OSC_PLLFAC_gp);
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54 | CLKSYS_Prescalers_Config( CLK_PSADIV_1_gc, CLK_PSBCDIV_1_1_gc ) ;
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55 | OSC.CTRL |= OSC_PLLEN_bm;
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56 | while( (OSC.STATUS & OSC_PLLRDY_bm) == 0){
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57 | //nop
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58 | }
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59 | CLK.CTRL = CLK_SCLKSEL_PLL_gc;
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60 |
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61 | CLKSYS_Disable(OSC_RC2MEN_bm);
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62 | CLKSYS_Disable(OSC_RC32MEN_bm);
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63 | }
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64 |
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65 | void PLL_init ( void )
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66 | {
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67 | //OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | 0x06;
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68 | OSC.PLLCTRL = OSC_PLLSRC_RC32M_gc | 0x04;
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69 | OSC.CTRL |= OSC_PLLEN_bm;
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70 | while (!(OSC.STATUS & OSC_PLLRDY_bm));
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71 | CCP = CCP_IOREG_gc;
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72 | CLK.CTRL = CLK_SCLKSEL_PLL_gc;
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73 | }
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