lx9_FT245_0.vhd

library ieee;

use ieee.std_logic_1164.all;

use IEEE.numeric_std.all;

-- synthesis translate_off

LIBRARY XilinxCoreLib;

-- synthesis translate_on

library unisim;

use unisim.vcomponents.all;

entity lx9_FT245 is port(

  CLK: in std_logic;

  D: inout std_logic_vector(7 downto 0);

  RXF: in std_logic; --when high do not read

  TXE: in std_logic; --when high do not write

  RD: out std_logic;

  WR: out std_logic;

  SIWU: out std_logic;

  CLKOUT: in std_logic;

  OE: out std_logic;

  PWRSAV: out std_logic;

  ACBUS8: out std_logic;

  ACBUS9: out std_logic;

  RST: out std_logic;

  PIN: out std_logic_vector(26 downto 3);

  LED: out std_logic_vector(1 downto 0);

  BTN: in std_logic);

end lx9_FT245;

architecture behav of lx9_FT245 is

component FIFO_ft232h is

Port (

  clk : in std_logic;

  rd: in std_logic;

  wr: in std_logic;

  data_in : in std_logic_vector(175 downto 0);

  data_out : out std_logic_vector(175 downto 0);

  full: out std_logic;

  empty: out std_logic);

end component;

signal blinkcounter_50: unsigned(25 downto 0):=(others => '0');

signal blinkcounter_60: unsigned(25 downto 0):=(others => '0');

signal bytecounter: unsigned(7 downto 0):=(others => '0');

signal counter_1ms: integer range 0 to 49:=0;

signal send_counter: integer range 0 to 21:=21;

signal fifo_in, fifo_out, send_data: std_logic_vector(175 downto 0):=(others => '0');

signal bytes_send: std_logic_vector(175 downto 0):=(others => '0');--:=x"000102030405060708090A0B0C0D0E0F1011121314";

signal fifo_empty,fifo_full,fifo_wr,fifo_rd_60,fifo_rd: std_logic:='0';

signal state: integer range 0 to 4:=0;

begin

f0: FIFO_ft232h Port map(

  clk => CLK,

  rd => fifo_rd,

  wr => fifo_wr,

  data_in => fifo_in,

  data_out => fifo_out,

  full => fifo_full,

  empty => fifo_empty);

RD <= '1';

SIWU <= '1';

OE <= '1';

PWRSAV <= 'Z';

ACBUS8 <= 'Z';

ACBUS9 <= 'Z';

RST <= '1';

PIN(3) <= CLKOUT;

PIN(4) <= TXE;

PIN(5) <= '0';

PIN(6) <= fifo_full;

PIN(7) <= '0';

PIN(26 downto 9) <= (others => '0');

LED(0) <= blinkcounter_50(25);

LED(1) <= blinkcounter_60(25);

fifo_in <= bytes_send;

process 

variable sr_rd_50 : std_logic_vector (1 downto 0) := "00";

begin

  wait until rising_edge(CLK);

  blinkcounter_50 <= blinkcounter_50 +1;

  counter_1ms <= counter_1ms+1;

  if counter_1ms = 49 then

    counter_1ms <= 0;

  end if;

  --- data ---

  if counter_1ms < 22 then

    bytecounter <= bytecounter +1;

    bytes_send <= bytes_send(167 downto 0) & std_logic_vector(bytecounter);

  end if;

  --- write ---

  fifo_wr <= '0';

  if counter_1ms = 32 then

    fifo_wr <= '1';

  end if;

  --- read ---

    sr_rd_50 := sr_rd_50(0) & fifo_rd_60;

    fifo_rd <= not sr_rd_50(1) and sr_rd_50(0);

end process;

process begin

  wait until rising_edge(CLKOUT);

  blinkcounter_60 <= blinkcounter_60 +1;

  fifo_rd_60 <= '0';

  if state = 0 then

    if fifo_empty = '0' then

      fifo_rd_60 <= '1';

      send_data <= fifo_out;

      state <= 1;

    end if;

  elsif state = 1 then

    fifo_rd_60 <= '1';

    send_data <= fifo_out;

    state <= 2;

  elsif state = 2 then

    fifo_rd_60 <= '0';

    send_data <= fifo_out;

    state <= 3;

  elsif state = 3 then

    fifo_rd_60 <= '0';

    send_data <= fifo_out;

    if TXE = '0' then

      send_counter <= 21;

      state <= 4;

      WR <= '0';

      PIN(8) <= '0';

    end if;

  elsif state = 4 then

    if send_counter = 0 then

      WR <= '1';

      PIN(8) <= '1';

    end if;

    if TXE = '0' and send_counter > 0 then

      send_counter <= send_counter-1;

    end if;

    if send_counter = 0 then

      WR <= '1';

      PIN(8) <= '1';

      state <= 0;

    end if;

  end if;

end process;

D <= send_data(send_counter*8 +7 downto send_counter*8) when state = 4 else "00000000";

end behav;