lx9_FT245_bench.vhd

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

use IEEE.std_logic_textio.all;

use STD.textio.all;

use IEEE.numeric_std.all;

ENTITY lx9_FT245_bench IS

END lx9_FT245_bench;

ARCHITECTURE behavior OF lx9_FT245_bench IS 

COMPONENT lx9_FT245 PORT(

  CLK : IN  std_logic;

  D : INOUT  std_logic_vector(7 downto 0);

  RXF : IN  std_logic;

  TXE : IN  std_logic;

  RD : OUT  std_logic;

  WR : OUT  std_logic;

  SIWU : OUT  std_logic;

  CLKOUT : IN  std_logic;

  OE : OUT  std_logic;

  PWRSAV : OUT  std_logic;

  ACBUS8 : OUT  std_logic;

  ACBUS9 : OUT  std_logic;

  RST : OUT  std_logic;

  PIN : OUT  std_logic_vector(26 downto 3);

  LED : OUT  std_logic_vector(1 downto 0);

  BTN : IN  std_logic);

END COMPONENT;

--Inputs

signal CLK : std_logic := '0';

signal RXF : std_logic := '0';

signal TXE : std_logic := '0';

signal CLKOUT : std_logic := '0';

signal BTN : std_logic := '0';

--BiDirs

signal D : std_logic_vector(7 downto 0);

--Outputs

signal RD : std_logic;

signal WR : std_logic;

signal SIWU : std_logic;

signal OE : std_logic;

signal PWRSAV : std_logic;

signal ACBUS8 : std_logic;

signal ACBUS9 : std_logic;

signal RST : std_logic;

signal PIN : std_logic_vector(26 downto 3);

signal LED : std_logic_vector(1 downto 0);

-- Clock period definitions

constant CLK_period : time := 20 ns;

constant CLKOUT_period : time := 16.66 ns;

signal D_old_u, D_u : unsigned(7 downto 0):=(others => '0');

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: lx9_FT245 PORT MAP(

  CLK => CLK,

  D => D,

  RXF => RXF,

  TXE => TXE,

  RD => RD,

  WR => WR,

  SIWU => SIWU,

  CLKOUT => CLKOUT,

  OE => OE,

  PWRSAV => PWRSAV,

  ACBUS8 => ACBUS8,

  ACBUS9 => ACBUS9,

  RST => RST,

  PIN => PIN,

  LED => LED,

  BTN => BTN);

CLK_process :process begin

  CLK <= '0';

  wait for CLK_period/2;

  CLK <= '1';

  wait for CLK_period/2;

  end process;

CLKOUT_process :process begin

  CLKOUT <= '0';

  wait for CLKOUT_period/2;

  CLKOUT <= '1';

  wait for CLKOUT_period/2;

  end process;

stim_proc: process begin    

  wait for 1.815 us;

  TXE <= '1';

  wait for 200 ns;

  TXE <= '0';

    wait for CLK_period*10;

    wait;

  end process;

write_io: process

  file my_output : TEXT open WRITE_MODE is "file_io.txt";

  variable my_line : LINE;

  variable whatsTheTime : time;

begin    

  wait until rising_edge(CLKOUT);

  if WR = '0' then

    D_old_u <= D_u;

    D_u <= unsigned(D);

    if D_u /= D_old_u +1 and D_u /= 0 then

      whatsTheTime := now;

      write(my_line,"FAIL - ");

      write(my_line,to_integer(D_old_u));

      write(my_line," - ");

      write(my_line,to_integer(D_u));

      write(my_line," - ");

      write(my_line,whatsTheTime);

      writeline(output,my_line);

    end if;

  end if;

  end process;

END;