fifo_ft232h.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity fifo_ft232h is

Port (

  clk : in std_logic;

  rd: in std_logic;

  wr: in std_logic;

  data_in : in std_logic_vector(175 downto 0);

  data_out : out std_logic_vector(175 downto 0);

  full: out std_logic;

  empty: out std_logic);

end fifo_ft232h;

architecture Behavioral of fifo_ft232h is

type speicher is array(0 to 2047) of std_logic_vector(175 downto 0);

signal memory : speicher;  

signal Schreibadresse, Leseadresse : unsigned (10 downto 0) := (others => '0');

signal full_buffer : std_logic:='0';

signal empty_buffer : std_logic:='1';

begin

empty <= empty_buffer;

full <= full_buffer;

process begin

wait until rising_edge(clk);

  if wr = '1' and rd = '0' and full_buffer = '0' then

    memory(to_integer(Schreibadresse)) <= data_in;

    Schreibadresse <= Schreibadresse + 1;

    empty_buffer <= '0';

    if Leseadresse = Schreibadresse +1 then

      full_buffer <= '1';

    else

      full_buffer <= '0';

    end if;

  end if;

  if rd = '1' and wr = '0' and empty_buffer = '0' then

    data_out <= memory(to_integer(Leseadresse));

    Leseadresse <= Leseadresse + 1;

    full_buffer <= '0';

    if Leseadresse +1 = Schreibadresse then

      empty_buffer <= '1';

    else

      empty_buffer <= '0';

    end if;

  end if;

  if rd = '1' and wr = '1' and empty_buffer = '0' then

    data_out <= memory(to_integer(Leseadresse));

    memory(to_integer(Schreibadresse)) <= data_in;

    Leseadresse <= Leseadresse + 1;

    Schreibadresse <= Schreibadresse + 1;

  end if;

end process;

end Behavioral;