1 | /*
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2 | Copyright (c) 2007 Stefan Engelke <mbox@stefanengelke.de>
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3 | */
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4 |
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5 | /* Memory Map */
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6 | #define CONFIG 0x00
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7 | #define EN_AA 0x01
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8 | #define EN_RXADDR 0x02
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9 | #define SETUP_AW 0x03
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10 | #define SETUP_RETR 0x04
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11 | #define RF_CH 0x05
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12 | #define RF_SETUP 0x06
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13 | #define STATUS 0x07
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14 | #define OBSERVE_TX 0x08
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15 | #define CD 0x09
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16 | #define RX_ADDR_P0 0x0A
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17 | #define RX_ADDR_P1 0x0B
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18 | #define RX_ADDR_P2 0x0C
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19 | #define RX_ADDR_P3 0x0D
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20 | #define RX_ADDR_P4 0x0E
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21 | #define RX_ADDR_P5 0x0F
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22 | #define TX_ADDR 0x10
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23 | #define RX_PW_P0 0x11
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24 | #define RX_PW_P1 0x12
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25 | #define RX_PW_P2 0x13
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26 | #define RX_PW_P3 0x14
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27 | #define RX_PW_P4 0x15
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28 | #define RX_PW_P5 0x16
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29 | #define FIFO_STATUS 0x17
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30 | #define DYNPD 0x1C
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31 |
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32 | /* Bit Mnemonics */
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33 |
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34 | /* configuratio nregister */
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35 | #define MASK_RX_DR 6
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36 | #define MASK_TX_DS 5
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37 | #define MASK_MAX_RT 4
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38 | #define EN_CRC 3
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39 | #define CRCO 2
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40 | #define PWR_UP 1
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41 | #define PRIM_RX 0
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42 |
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43 | /* enable auto acknowledgment */
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44 | #define ENAA_P5 5
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45 | #define ENAA_P4 4
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46 | #define ENAA_P3 3
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47 | #define ENAA_P2 2
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48 | #define ENAA_P1 1
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49 | #define ENAA_P0 0
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50 |
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51 | /* enable rx addresses */
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52 | #define ERX_P5 5
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53 | #define ERX_P4 4
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54 | #define ERX_P3 3
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55 | #define ERX_P2 2
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56 | #define ERX_P1 1
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57 | #define ERX_P0 0
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58 |
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59 | /* setup of address width */
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60 | #define AW 0 /* 2 bits */
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61 |
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62 | /* setup of auto re-transmission */
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63 | #define ARD 4 /* 4 bits */
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64 | #define ARC 0 /* 4 bits */
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65 |
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66 | /* RF setup register */
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67 | #define PLL_LOCK 4
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68 | #define RF_DR 3
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69 | #define RF_PWR 1 /* 2 bits */
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70 |
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71 | /* general status register */
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72 | #define RX_DR 6
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73 | #define TX_DS 5
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74 | #define MAX_RT 4
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75 | #define RX_P_NO 1 /* 3 bits */
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76 | #define TX_FULL 0
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77 |
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78 | /* transmit observe register */
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79 | #define PLOS_CNT 4 /* 4 bits */
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80 | #define ARC_CNT 0 /* 4 bits */
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81 |
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82 | /* fifo status */
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83 | #define TX_REUSE 6
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84 | #define FIFO_FULL 5
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85 | #define TX_EMPTY 4
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86 | #define RX_FULL 1
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87 | #define RX_EMPTY 0
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88 |
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89 | /* dynamic length */
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90 | #define DPL_P0 0
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91 | #define DPL_P1 1
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92 | #define DPL_P2 2
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93 | #define DPL_P3 3
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94 | #define DPL_P4 4
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95 | #define DPL_P5 5
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96 |
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97 | /* Instruction Mnemonics */
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98 | #define R_REGISTER 0x00 /* last 4 bits will indicate reg. address */
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99 | #define W_REGISTER 0x20 /* last 4 bits will indicate reg. address */
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100 | #define REGISTER_MASK 0x1F
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101 | #define R_RX_PAYLOAD 0x61
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102 | #define W_TX_PAYLOAD 0xA0
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103 | #define FLUSH_TX 0xE1
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104 | #define FLUSH_RX 0xE2
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105 | #define REUSE_TX_PL 0xE3
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106 | #define ACTIVATE 0x50
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107 | #define R_RX_PL_WID 0x60
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108 | #define NOP 0xFF
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