apb_register.vhd

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

entity apb_register is

    port (

        clk: in std_logic;

        resetn: in std_logic;

        PENABLE: in std_logic;

        PSELx: in std_logic;

        PREADY: out std_logic;

        PSLVERR: out std_logic;

        PADDR: in std_logic_vector(7 downto 0);

        PWRITE: in std_logic;

        PWDATA: in std_logic_vector(7 downto 0);

        PRDATA: out std_logic_vector(7 downto 0)

    );

end entity apb_register;

architecture one of apb_register is

type t_array_apb_regs is array(0 to 4-1) of std_logic_vector(7 downto 0);

signal apb_regs: t_array_apb_regs;

begin

PREADY<='1';

PSLVERR<='0';

APB_REGISTER_APB_REGISTER_CLCKED: process (clk) is

begin

    if rising_edge(clk) then

        if (not(resetn))='1' then

            for k in 0 to 4-1 loop

                apb_regs(k) <= "00000000";

            end loop;

        else

            if ((PWRITE) and (PSELx) and (PENABLE))='1' then

                apb_regs(to_integer(unsigned(PADDR(8-1 downto 2)))) <= PWDATA;

            end if;

        end if;

        if ((not (PWRITE)) and (PSELx))='1' then

            PRDATA <= apb_regs(to_integer(unsigned(PADDR(8-1 downto 2))));

        end if;

    end if;

end process APB_REGISTER_APB_REGISTER_CLCKED;

end architecture one;