FP_Setup_Type.vhd


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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use ieee.numeric_std.ALL;

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entity FP_Setup is

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  generic

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  (  ClockDiv    : integer := 7              -- Frequenzen: FP_DClk = Clock / ClockDiv

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  );

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  port

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  (  Clock      : in std_logic;

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    FP_DIn      : in std_logic;              -- SPI Data in

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    FP_DClk      : out std_logic;            -- SPI Clock

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    FP_DStb      : out std_logic;            -- SPI Data strobe

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    FP_DOut      : out std_logic;            -- SPI Data out

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    CY7_DIn      : in std_logic;              -- SPI Data in

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    CY7_DClk    : in std_logic;              -- SPI Clock

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    CY7_DStb    : in std_logic;              -- SPI Data strobe

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    CY7_DOut    : out std_logic;            -- SPI Data out

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    SampleRate    : out std_logic_vector (4 downto 0);  -- -> I2S_Master.vhd

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    NoOfChannels  : out std_logic_vector (4 downto 0);  -- 0..31: 1..32 Channels used

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    SelChannel    : out std_logic_vector (4 downto 0);  -- Listen to Channel 1..32

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    SelMono      : out std_logic;            -- Listen to Channel Mono

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    SetupChanged  : out std_logic              -- SampleRate or NoOfChannels changed

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  );

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end FP_Setup ;

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architecture Default of FP_Setup is

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  type   SLV_CY7_Bytes is array(integer range <>) of std_logic_vector(7 downto 0);

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  signal Init        : boolean;

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  signal ClockCount    : integer range 0 to ClockDiv;

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  signal SPI_Status    : integer range 0 to 24;        -- 24 Data Bits + Strobe

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  signal MuxCount      : std_logic_vector(2 downto 0);      -- Multiplex 8 7-Segment Digits

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  signal StateTa1      : integer range 0 to 2;          -- 0: Ruhe, 1: Ta gedrückt, 2: Sw gedreht

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  signal InputShift    : std_logic_vector(5 downto 0);

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  signal InputReg      : std_logic_vector(5 downto 0);      -- Bit 5..0: Sw1, Sw2, Ta1, Ta2

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  signal InputReg2    : std_logic_vector(5 downto 0);      -- Bit 5..0: Sw1, Sw2, Ta1, Ta2

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  signal CY7_ClkDly    : std_logic_vector(1 to 2);              -- 

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  signal CY7_DInDly    : std_logic_vector(1 to 2);              -- 

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  signal CY7_StbDly    : std_logic_vector(1 to 2);              -- 

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  signal CY7_InShift    : std_logic_vector(31 downto 0);    --

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  signal CY7_InReg    : std_logic_vector(31 downto 0);    --

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  signal CY7_OutShift    : std_logic_vector(31 downto 0);    --

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  -- Einstellungen:

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  signal SRate      : std_logic_vector(4 downto 0);      -- -> I2S_Master.vhd

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  signal NChannels    : std_logic_vector(4 downto 0);      -- 0..31: Max. 32 Channels used

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  signal SChannel      : std_logic_vector(4 downto 0);      -- 0..31: Listen to Channel 1..32

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  signal SMono      : std_logic;              -- Listen to Channel Mono

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  -- Für die Anzeige:

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  signal NumVal32      : std_logic_vector(7 downto 0);      -- NChannels + 1, SChannel + 1, binär

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  signal BCD_Val32    : std_logic_vector(7 downto 0);      -- NChannels + 1, SChannel + 1, BCD

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  signal BCD_ValSR    : std_logic_vector(15 downto 0);    -- Sample Rate BCD

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  signal DP_SR      : integer range 2 to 5;          -- Position des Dezimalpunkts SR

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  signal BCD7SegIn    : std_logic_vector(3 downto 0);      -- Eingabe 7-Segment Encoder

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  signal BCD7SegOut    : std_logic_vector(7 downto 0);      -- Ausgabe 7-Segment Encoder

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begin

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  CY7_Communication : process (Clock) begin

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    -- Datenblatt: At both low and high speed in Mode 0, data on RXD0

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    -- is sampled two CLKOUT cycles before the rising clock edge on TXD0.

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    if Clock = '1' and Clock'event then

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      CY7_ClkDly <= CY7_DClk & CY7_ClkDly(1);

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      CY7_DInDly <= CY7_DIn & CY7_DInDly(1);

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      CY7_StbDly <= CY7_DStb & CY7_StbDly(1);

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      if CY7_ClkDly = "10" then

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        CY7_InShift <= CY7_DInDly(2) & CY7_InShift(CY7_InShift'high downto 1);

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      end if;

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      if CY7_StbDly = "10"  then

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        CY7_InReg <= CY7_InShift;

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        CY7_OutShift <= CY7_InShift;

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      end if;

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      if CY7_ClkDly = "10" then

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        CY7_OutShift <= '0' & CY7_OutShift(CY7_OutShift'high downto 1);

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      end if;

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      CY7_DOut <= CY7_OutShift(0);

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    end if;

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  end process CY7_Communication;

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  SPI_and_Settings : process (Clock) begin

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    if Clock = '1' and Clock'event then

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      if not Init then

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        NChannels <= (others => '1');

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        Init <= true;

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      end if;

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      ClockCount <= ClockCount + 1;

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      if ClockCount = ClockDiv / 2 then

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        FP_DStb <= '0';

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        FP_DClk <= '1';

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      end if;

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      if ClockCount = 0 then

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        SetupChanged <= '0';

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        if InputReg(5) = '0' then

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          -- Taste Sw1 (Kanäle) gedrückt: Umschalten Mono/Stero bei Listen to Channel?

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          if StateTa1 < 2 then

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            StateTa1 <= 1;

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          end if;

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        else

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          if StateTa1 = 1 then

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            SMono <= not SMono;

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          end if;

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          StateTa1 <= 0;

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        end if;

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        if SPI_Status = 24 then

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          -- Restart SPI-Tx

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          SPI_Status <= 0;

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          FP_DStb <= '1';

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          MuxCount <= std_logic_vector(unsigned(MuxCount) + 1);          -- Mux Digit 0..7

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        else

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          -- Continue SPI-Tx

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          SPI_Status <= SPI_Status + 1;

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          FP_DClk <= '0';

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          InputShift <= InputShift(4 downto 0) & FP_DIn;

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          if SPI_Status = 8 then

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            -- 1 Byte data input

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            InputReg <= InputShift;

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            InputReg2 <= InputReg;

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            if InputReg(4) = '0' then

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              -- Taste Sw2 (Sample Rate) gedrückt

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              case InputReg2(1 downto 0) & InputReg(1 downto 0) is

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                -- Sample Rate

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                when "0100" | "1011" => if unsigned(SRate) > 0 then

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                              SRate <= std_logic_vector(unsigned(SRate) - 1);

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                              SetupChanged <= '1';

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                              if unsigned(SRate) = 4 then

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                                -- 128 kHz überspringen

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                                SRate <= "00001";

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                              elsif SRate(1 downto 0) = "00" then

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                                -- 8, 16, 32, 64 kHz nicht mit 22 MHz Oszillator

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                                SRate <= std_logic_vector(unsigned(SRate) - 2);

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                              end if;

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                            end if;

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                when "0001" | "1110" => if unsigned(SRate) < 18 then

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                              SRate <= std_logic_vector(unsigned(SRate) + 1);

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                              SetupChanged <= '1';

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                              if unsigned(SRate) = 1 then

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                                -- 128 kHz überspringen

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                                SRate <= "00100";

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                              elsif SRate(1 downto 0) = "10" then

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                                -- 8, 16, 32, 64 kHz nicht mit 22 MHz Oszillator

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                                SRate <= std_logic_vector(unsigned(SRate) + 2);

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                              end if;

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                            end if;

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                when others => null;

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              end case;

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            end if;

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            if InputReg(5) = '0' then

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              -- Taste Sw1 (Kanäle) gedrückt

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              case InputReg2(3 downto 2) & InputReg(3 downto 2) is

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                -- Number of Channels

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                when "0100" | "1011" => if unsigned(NChannels) < 31 then 

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                              NChannels <= std_logic_vector(unsigned(NChannels) + 1);

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                              SetupChanged <= '1';

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                            end if;

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                            StateTa1 <= 2;        -- Keine Mono/Stereo-Umschaltung

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                when "0001" | "1110" => if unsigned(NChannels) > 0 then 

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                              NChannels <= std_logic_vector(unsigned(NChannels) - 1);

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                              SetupChanged <= '1';

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                              if SChannel > NChannels then 

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                                SChannel <= NChannels;

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                              end if;

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                            end if;

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                            StateTa1 <= 2;        -- Keine Mono/Stereo-Umschaltung

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                when others => null;

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              end case;

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            else

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              -- Taste Sw1 (Kanäle) gelöst

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              case InputReg2(3 downto 2) & InputReg(3 downto 2) is

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                -- Selected Channel

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                when "0100" | "1011" =>  if SChannel < NChannels then 

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                              SChannel <= std_logic_vector(unsigned(SChannel) + 1);

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                            end if;

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                when "0001" | "1110" => if unsigned(SChannel) > 0 then 

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                              SChannel <= std_logic_vector(unsigned(SChannel) - 1);

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                            end if;

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                when others => null;

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              end case;

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            end if;

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            if SChannel > NChannels then 

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              SChannel <= NChannels;

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            end if;

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          end if;

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        end if;

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      end if;

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    end if;

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  end process SPI_and_Settings;

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  with to_integer(unsigned(SRate)) select

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  BCD_ValSR <=  x"1920" when 0,

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          x"1764" when 1,

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          x"f960" when 4,

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          x"f882" when 5,

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          x"f640" when 6,

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          x"f480" when 8,

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          x"f441" when 9,

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          x"f320" when 10,

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          x"f240" when 12,

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          x"2205" when 13,

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          x"f160" when 14,

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          x"f120" when 16,

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          x"1102" when 17,

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          x"ff80" when others;

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  with to_integer(unsigned(SRate)) select

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    DP_SR <=   3 when 13 | 17,

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          4 when others;

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  NumVal32 <= "000" & std_logic_vector(unsigned(NChannels) + 1) when unsigned(MuxCount) < 4

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       else "000" & std_logic_vector(unsigned(SChannel) + 1);

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  BCD_Val32 <= std_logic_vector(unsigned(NumVal32) +  0) when unsigned(NumVal32) < 10

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      else std_logic_vector(unsigned(NumVal32) +  6) when unsigned(NumVal32) < 20

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      else std_logic_vector(unsigned(NumVal32) + 12) when unsigned(NumVal32) < 30

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      else std_logic_vector(unsigned(NumVal32) + 18);

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  BCD7SegIn <= BCD_Val32(3 downto 0)   when unsigned(MuxCount) = 1 or unsigned(MuxCount) = 7

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      else BCD_ValSR(15 downto 12) when unsigned(MuxCount) = 2

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      else BCD_ValSR(11 downto 8)  when unsigned(MuxCount) = 3

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      else BCD_ValSR(7 downto 4)   when unsigned(MuxCount) = 4

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      else BCD_ValSR(3 downto 0)   when unsigned(MuxCount) = 5

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      else x"f"           when unsigned(BCD_Val32(7 downto 4)) = 0  -- 0 & 6

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      else BCD_Val32(7 downto 4);          -- 0 & 6

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  with to_integer(unsigned(BCD7SegIn)) select

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    BCD7SegOut <=  x"fc" when 0,

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            x"60" when 1,

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            x"da" when 2,

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            x"f2" when 3,

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            x"66" when 4,

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            x"b6" when 5,

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            x"be" when 6,

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            x"e0" when 7,

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            x"fe" when 8,

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            x"f6" when 9,

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            x"00" when others;

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  FP_DOut <=  SMono when (unsigned(MuxCount) = 7) and (SPI_Status = 9) else                -- Dez. Punkt für SelMono

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        '1' when (to_integer(unsigned(MuxCount)) = DP_SR) and (SPI_Status = 9) else              -- Dez. Punkt für Sample Rate

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        BCD7SegOut(SPI_Status - 9) when (SPI_Status >= 9) and (SPI_Status <= 16) else  --  8..15: Segm.-LEDs

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        '0' when (SPI_Status) - 17 = to_integer(unsigned(not MuxCount)) else                  -- 16..23: Anode driver on

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        '1';                                      --  0..7 and Anode driver off 

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  SampleRate <= SRate;

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  NoOfChannels <= NChannels;

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  SelChannel <= SChannel;

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  SelMono <= SMono;

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end Default;