moving_average.vhd

-- FMT FAU Erlangen -----------------------------------------------

-- moving_average:                                               --

-- this module generates a parametrized moving average over      --

-- two's complement dividable ranges with an parallel in parallel--

-- out data set.                                                 --

-- For the usage just set your desired data and shift width as a --

-- Bit statement.                                                --

--                                                               --

-------------------------------------------------------------------

-- Programming style ----------------------------------------------

-- parameter prefix | description                                --

-- g_               | generic, for entity declatation            --

-- i_               | input, for entity declatation              --

-- o_               | output, for entity declatation             --

-- io_              | in-/output, for entity declatation         --

-- c_               | constant, for architecture declatation     --

-- t_               | type, for architecture declatation         --

-- w_               | wire, used for internal signals            --

-- tb_              | testbench, used for internal signals       --

-- p_               | process, used for process labels           --

-- inst_            | instantiate, used fpr component instan-    --

--                    tiation                                    --

--                                                               --

-- parameter suffix | description                                --

-- _reg             | regular signal, for register (synchron)    --

-- _next            | next signal, for register (asynchron)      --

-- _s               | synchronised                               --

--                                                               --

-------------------------------------------------------------------

-- Revision History -----------------------------------------------

-- Version: | Author:   | Mod. Date:    | Changes Made:          --

-- 0.1      | Koehnen   | 05/09/17:     | Module developement    --

-------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.math_real.all;

entity moving_average is

  generic(

    g_data_width  : positive := 4;

    g_shift_width  : positive := 2

    );

  port(

    i_clk  : in  std_logic;

    i_clear  : in  std_logic;

    i_data  : in  std_logic_vector(g_data_width-1 downto 0);

    o_data  : out std_logic_vector(g_data_width-1 downto 0)

    );

end entity moving_average;

architecture behavioral of moving_average is

  -- constants

  constant c_shift_range : integer := integer(2.0**real(g_shift_width));

  -- typedeclaration

  type  t_Q_temp is array (0 to c_shift_range-1) of std_logic_vector(g_data_width-1 downto 0); 

  type  t_sum is array (0 to c_shift_range) of unsigned(g_data_width+g_shift_width-1 downto 0);

  -- g_shift_width also increments the length of guardbits which needed for the summation

  -- evidence: ceil(log2(2**g_shift_width)) == g_shift_width

  -- signals

  signal  w_Q_temp : t_Q_temp;

  signal  w_sum  : t_sum := (others => (others => '0'));

  -- components

  component shift_reg_pipo is

    generic(

      data_width : positive := 4

      );

    port(

      clk : in std_logic;

      clear : in std_logic;

      D: in std_logic_vector(g_data_width-1 downto 0);

      Q: out std_logic_vector(g_data_width-1 downto 0)

      );

  end component shift_reg_pipo;

begin

  -- parallel in parallel out (PIPO) shift register 

  p_shift_gen : for I in 1 to c_shift_range-1 generate

    pipo_I : shift_reg_pipo

    generic map(

      data_width => g_data_width

      )

    port map(

      clk => i_clk,

      clear => i_clear,

      D  => w_Q_temp(I-1), --  first element in loop is w_Q_temp(0)

      Q  => w_Q_temp(I)

      );

  end generate p_shift_gen;

  -- summation

  p_sum_gen : for I in 1 to c_shift_range generate

    w_sum(I) <= w_sum(I-1) + unsigned(w_Q_temp(I-1)); -- summs up every shifted value

  end generate p_sum_gen;

  -- connect shift register

  w_Q_temp(0) <= i_data(g_data_width-1 downto 0); -- allocates first data element to array

  -- divide/shift Bits

  o_data <= std_logic_vector(w_sum(c_shift_range)(g_data_width+g_shift_width-1 downto g_shift_width)); -- trimm last sum vector to devide by k*2

end architecture behavioral;