moving_average_tb.vhd


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-- FMT FAU Erlangen -----------------------------------------------

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-- moving_average_tb:                                            --

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-- verify the moving_average module with an sinusodial oscilation--

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-- The generic parameters can be modified in the constant        --

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-- section.                                                      --

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--                                                               --

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-------------------------------------------------------------------

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-- Programming style ----------------------------------------------

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-- parameter prefix | description                                --

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-- g_               | generic, for entity declatation            --

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-- i_               | input, for entity declatation              --

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-- o_               | output, for entity declatation             --

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-- io_              | in-/output, for entity declatation         --

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-- c_               | constant, for architecture declatation     --

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-- t_               | type, for architecture declatation         --

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-- w_               | wire, used for internal signals            --

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-- tb_              | testbench, used for internal signals       --

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-- p_               | process, used for process labels           --

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-- inst_            | instantiate, used fpr component instan-    --

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--                    tiation                                    --

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--                                                               --

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-- parameter suffix | description                                --

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-- _reg             | regular signal, for register (synchron)    --

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-- _next            | next signal, for register (asynchron)      --

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-- _s               | synchronised                               --

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--                                                               --

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-------------------------------------------------------------------

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-- Revision History -----------------------------------------------

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-- Version: | Author:   | Mod. Date:    | Changes Made:          --

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-- 0.1      | Koehnen   | 05/09/17:     | Module developement    --

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-------------------------------------------------------------------

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.numeric_std.all;

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entity moving_average_tb is

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end entity moving_average_tb;

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architecture behavioral of moving_average_tb is

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  -- constants

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  constant tb_clk_periode : time := 20 ns; -- 50 MHz

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  constant tb_g_phasewidth    : positive := 6; -- recommended maximum: 22

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  constant tb_g_ampliduewidth : positive := 6; -- describes also input data width of moving average module

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  constant tb_g_data_width  : positive := 6;   -- need to be the same as tb_g_ampliduewidth

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  constant tb_g_shift_width : positive := 8;   -- needs at least to be one bit higher then tb_g_phasewidth to observe more then one periode

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  -- signals

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  signal tb_i_clk       : std_logic := '0';

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  signal tb_i_reset     : std_logic := '0';

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  signal tb_i_step      : std_logic_vector(tb_g_phasewidth/2 downto 0) := std_logic_vector(to_unsigned(1,tb_g_phasewidth/2+1));

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  signal tb_i_step_size : std_logic_vector(tb_g_phasewidth/2 downto 0) := (others => '0');

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  signal tb_o_sin_data  : std_logic_vector(tb_g_ampliduewidth-1 downto 0);

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  signal tb_o_moving_average  : std_logic_vector(tb_g_ampliduewidth-1 downto 0);

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  signal tb_o_trigger   : std_logic;

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  -- components

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  component sineLUT is

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  generic(

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    g_phasewidth    : positive := 9;

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    g_ampliduewidth : positive := 14

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  );

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  port(

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    i_clk      : in  std_logic;

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    i_clk_en   : in  std_logic;

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    i_reset    : in  std_logic;

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    i_step_size: in  std_logic_vector(g_phasewidth/2 downto 0) := (others => '0');

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    i_step     : in  std_logic_vector(g_phasewidth/2 downto 0) := "01";

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    o_sin_data : out std_logic_vector(g_ampliduewidth-1 downto 0);

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    o_trigger  : out std_logic

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    );

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  end component sineLUT;

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  component moving_average is

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  generic(

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    g_data_width  : positive := 4;

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    g_shift_width  : positive := 2

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    );

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  port(

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    i_clk  : in  std_logic;

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    i_clear  : in  std_logic;

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    i_data  : in  std_logic_vector(g_data_width-1 downto 0);

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    o_data  : out std_logic_vector(g_data_width-1 downto 0)

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    );

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  end component moving_average;

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begin

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  tb_i_reset <= '1', '0' after 10 ns;

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  p_clock : process

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  begin

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    tb_i_clk <= '1';

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    wait for tb_clk_periode/2;

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    tb_i_clk <= '0';

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    wait for tb_clk_periode/2;

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  end process p_clock;

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  inst_NCO : sineLUT

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    generic map(

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      g_phasewidth    => tb_g_phasewidth,

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      g_ampliduewidth => tb_g_ampliduewidth

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    )

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    port map(

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      i_clk      => tb_i_clk,

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      i_clk_en   => '1',

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      i_reset    => tb_i_reset,

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      i_step     => tb_i_step,

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      i_step_size=> tb_i_step_size,

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      o_sin_data => tb_o_sin_data,

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      o_trigger  => tb_o_trigger

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      );

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  inst_DUT : moving_average

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    generic map(

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      g_data_width  => tb_g_data_width,

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      g_shift_width  => tb_g_shift_width

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      )

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    port map(

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      i_clk  => tb_i_clk,

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      i_clear => tb_i_reset,

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      i_data  => tb_o_sin_data,

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      o_data  => tb_o_moving_average

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      );

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end architecture behavioral;