main.c


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#include <stdint.h>

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/************* Takt ************************************/

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#define F_Quarz       8000000        

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#define F_Platform   72000000        

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#define F_APB        36000000        

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/************* Register defs ***************************/

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#define FLASH_ACR     (*((volatile uint32_t *) 0x40022000)) // 

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#define PWR     0x40007000 // Power control PWR Section 4.4.3 on page 66

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#define PWR_CR       (*((volatile uint32_t *) (PWR + 0)))

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#define SYST_RVR    (*((volatile uint32_t *) 0xE000E014)) 

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#define SYST_CSR    (*((volatile uint32_t *) 0xE000E010)) 

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/************* GPIO and AFIO register ******************/

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#define AFIO    0x40010000 // AFIO

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#define AFIO_MAPR    (*((volatile uint32_t *) (AFIO + 0x04)))

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#define GPIOA   0x40010800 // GPIO Port A Section 8.5 on page 169

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#define GPIOB   0x40010C00 // GPIO Port B Section 8.5 on page 169

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#define GPIOC   0x40011000 // GPIO Port C Section 8.5 on page 169

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#define GPIOD   0x40011400 // GPIO Port D Section 8.5 on page 169

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#define GPIOA_CRL   (*((volatile uint32_t *) (GPIOA + 0x00)))

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#define GPIOA_CRH   (*((volatile uint32_t *) (GPIOA + 0x04)))

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#define GPIOA_IDR   (*((volatile uint32_t *) (GPIOA + 0x08)))

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#define GPIOA_ODR   (*((volatile uint32_t *) (GPIOA + 0x0C))) 

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#define GPIOA_BSRR  (*((volatile uint32_t *) (GPIOA + 0x10)))

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#define GPIOA_BRR   (*((volatile uint32_t *) (GPIOA + 0x14)))

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#define GPIOA_LCKR  (*((volatile uint32_t *) (GPIOA + 0x18)))

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#define GPIOB_CRL   (*((volatile uint32_t *) (GPIOB + 0x00)))

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#define GPIOB_CRH   (*((volatile uint32_t *) (GPIOB + 0x04)))

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#define GPIOB_IDR   (*((volatile uint32_t *) (GPIOB + 0x08)))

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#define GPIOB_ODR   (*((volatile uint32_t *) (GPIOB + 0x0C))) 

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#define GPIOB_BSRR  (*((volatile uint32_t *) (GPIOB + 0x10)))

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#define GPIOB_BRR   (*((volatile uint32_t *) (GPIOB + 0x14)))

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#define GPIOB_LCKR  (*((volatile uint32_t *) (GPIOB + 0x18)))

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#define GPIOC_CRL   (*((volatile uint32_t *) (GPIOC + 0x00)))

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#define GPIOC_CRH   (*((volatile uint32_t *) (GPIOC + 0x04)))

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#define GPIOC_IDR   (*((volatile uint32_t *) (GPIOC + 0x08)))

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#define GPIOC_ODR   (*((volatile uint32_t *) (GPIOC + 0x0C))) 

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#define GPIOC_BSRR  (*((volatile uint32_t *) (GPIOC + 0x10)))

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#define GPIOC_BRR   (*((volatile uint32_t *) (GPIOC + 0x14)))

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#define GPIOC_LCKR  (*((volatile uint32_t *) (GPIOC + 0x18)))

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#define GPIOD_CRL   (*((volatile uint32_t *) (GPIOD + 0x00)))

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#define GPIOD_CRH   (*((volatile uint32_t *) (GPIOD + 0x04)))

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#define GPIOD_IDR   (*((volatile uint32_t *) (GPIOD + 0x08)))

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#define GPIOD_ODR   (*((volatile uint32_t *) (GPIOD + 0x0C))) 

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#define GPIOD_BSRR  (*((volatile uint32_t *) (GPIOD + 0x10)))

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#define GPIOD_BRR   (*((volatile uint32_t *) (GPIOD + 0x14)))

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#define GPIOD_LCKR  (*((volatile uint32_t *) (GPIOD + 0x18)))

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/************* Reset and clock control (RCC) ************/

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#define RCC     0x40021000 // Reset and clock control Section 6.3.11 on page 103

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#define RCC_CR       (*((volatile uint32_t *) (RCC + 0)))

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#define RCC_CFGR     (*((volatile uint32_t *) (RCC + 4)))

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#define RCC_CIR      (*((volatile uint32_t *) (RCC + 8)))

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#define RCC_APB2RSTR (*((volatile uint32_t *) (RCC + 0x0C)))

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#define RCC_APB1RSTR (*((volatile uint32_t *) (RCC + 0x10)))

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#define RCC_AHBENR   (*((volatile uint32_t *) (RCC + 0x14)))

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#define RCC_APB2ENR  (*((volatile uint32_t *) (RCC + 0x18)))

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#define RCC_APB1ENR  (*((volatile uint32_t *) (RCC + 0x1C)))

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#define RCC_BDCR     (*((volatile uint32_t *) (RCC + 0x20)))

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#define RCC_CSR      (*((volatile uint32_t *) (RCC + 0x24)))

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#define RCC_AHBRSTR  (*((volatile uint32_t *) (RCC + 0x28)))

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#define RCC_CFGR2    (*((volatile uint32_t *) (RCC + 0x2C)))

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#define RCC_APB2ENR_SPI1EN                   (1U<<12)

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/************** Serial peripheral interface (SPI) **********/

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#define SPI1    0x40013000 // SPI1 Section 23.5 on page 627

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#define SPI1_CR1     (*((volatile uint32_t *) (SPI1 + 0x0)))

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#define SPI1_CR2     (*((volatile uint32_t *) (SPI1 + 0x4)))

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#define SPI1_SR      (*((volatile uint32_t *) (SPI1 + 0x8)))

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#define SPI1_DR      (*((volatile uint32_t *) (SPI1 + 0xC)))

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#define SPI1_CRCPR   (*((volatile uint32_t *) (SPI1 + 0x10)))

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#define SPI1_RXCRCR  (*((volatile uint32_t *) (SPI1 + 0x14)))

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#define SPI1_TXCRCR  (*((volatile uint32_t *) (SPI1 + 0x18)))

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#define SPI1_I2SCFGR (*((volatile uint32_t *) (SPI1 + 0x1C)))

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#define SPI1_I2SPR   (*((volatile uint32_t *) (SPI1 + 0x20)))

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#define SPI_CR1_CPHA                        (1<<0)

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#define SPI_CR1_CPOL                        (1<<1)

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#define SPI_CR1_MSTR                        (1<<2)

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#define SPI_CR1_BR_DIV2                     (0u << 3)

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#define SPI_CR1_BR_DIV4                     (1u << 3)

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#define SPI_CR1_BR_DIV8                     (2u << 3)

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#define SPI_CR1_BR_DIV16                    (3u << 3)

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#define SPI_CR1_BR_DIV32                    (4u << 3)

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#define SPI_CR1_BR_DIV64                    (5u << 3)

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#define SPI_CR1_BR_DIV128                   (6u << 3)

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#define SPI_CR1_BR_DIV256                   (7u << 3)

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#define SPI_CR1_SPE                         (1<<6)

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#define SPI_CR1_LSBFIRST                    (1<<7)

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#define SPI_CR1_SSI                         (1<<8)

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#define SPI_CR1_SSM                         (1<<9)

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#define SPI_CR1_RXONLY                      (1<<10)

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#define SPI_CR1_DFF                         (1<<11)

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#define SPI_CR1_CRCNEXT                     (1<<12)

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#define SPI_CR1_CRCEN                       (1<<13)

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#define SPI_CR1_BIDIOE                      (1<<14)

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#define SPI_CR1_BIDIMODE                    (1<<15)

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#define SPI_CR2_RXDMAEN                     (1<<0)

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#define SPI_CR2_TXDMAEN                     (1<<1)

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#define SPI_CR2_SSOE                        (1<<2)

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#define SPI_CR2_reserved1                   (1<<3)

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#define SPI_CR2_reserved2                   (1<<4)

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#define SPI_CR2_ERRIE                       (1<<5)

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#define SPI_CR2_RXNEIE                      (1<<6)

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#define SPI_CR2_TXEIE                       (1<<7)

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#define SPI_SR_RXNE                         (1<<0)

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#define SPI_SR_TXE                          (1<<1)

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#define SPI_SR_CHSIDE                       (1<<2)

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#define SPI_SR_UDR                          (1<<3)

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#define SPI_SR_CRCERR                       (1<<4)

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#define SPI_SR_MODF                         (1<<5)

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#define SPI_SR_OVR                          (1<<6)

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#define SPI_SR_BSY                          (1<<7)

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// -------------------- GPIOx_CRx bits --------------------                    

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#define  noPin      4     // floating input, reset state

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#define  ANALOG     0     /* analoger Eingang (oder Ausgang?) */ 

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#define  OUT_10     1     /* out, 10 MHz */ 

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#define  OUT_2      2     /* out,  2 MHz */ 

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#define  OUT_50     3     /* out, 50 MHz */ 

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#define  IN         4     /* digitaler Eingang */ 

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#define  OUT_10_OD  5     /* out, 10 MHz, OpenDrain */ 

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#define  OUT_2_OD   6     /* out,  2 MHz, OpenDrain */ 

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#define  OUT_50_OD  7     /* out, 50 MHz, OpenDrain */ 

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#define  IN_PUPD    8     /* digitaler Eingang, Pullup/down je nach GPIOx_ODR */ 

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#define  ALTF_10    9     /* Alternativ-Funktion, 10 MHz */ 

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#define  ALTF_2     10    /* Alternativ-Funktion,  2 MHz */ 

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#define  ALTF_50    11    /* Alternativ-Funktion, 50 MHz */ 

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#define  ALTF_10_OD 13    /* Alternativ-Funktion, 10 MHz, OpenDrain */ 

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#define  ALTF_2_OD  14    /* Alternativ-Funktion,  2 MHz, OpenDrain */ 

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#define  ALTF_50_OD 15    /* Alternativ-Funktion, 50 MHz, OpenDrain */ 

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// ---------------- Port A --------------------

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#define wf_PA0      OUT_2_OD      

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#define wf_PA1      OUT_2_OD      

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#define wf_PA2      OUT_2_OD      

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#define wf_PA3      OUT_2_OD      

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#define wf_PA4      OUT_10        

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#define wf_PA5      ALTF_50       

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#define wf_PA6      OUT_10        

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#define wf_PA7      ALTF_50       

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#define wf_PA8      noPin         

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#define wf_PA9      noPin         

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#define wf_PA10     noPin         

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#define wf_PA11     ALTF_50       

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#define wf_PA12     ALTF_50       

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#define wf_PA13     IN            

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#define wf_PA14     IN            

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#define wf_PA15     IN_PUPD       

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// ---------------- Port B --------------------

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#define wf_PB0      noPin         

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#define wf_PB1      noPin         

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#define wf_PB2      IN            

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#define wf_PB3      IN_PUPD       

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#define wf_PB4      OUT_2_OD      

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#define wf_PB5      OUT_2_OD      

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#define wf_PB6      OUT_2_OD      

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#define wf_PB7      OUT_2_OD      

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#define wf_PB8      ALTF_50_OD    

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#define wf_PB9      ALTF_50_OD    

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#define wf_PB10     OUT_2         

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#define wf_PB11     OUT_2         

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#define wf_PB12     OUT_2         

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#define wf_PB13     ALTF_50       

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#define wf_PB14     OUT_2         

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#define wf_PB15     ALTF_50       

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// ---------------- Port C --------------------

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#define wf_PC0      noPin           

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#define wf_PC1      noPin           

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#define wf_PC2      noPin           

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#define wf_PC3      noPin           

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#define wf_PC4      noPin           

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#define wf_PC5      noPin           

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#define wf_PC6      noPin           

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#define wf_PC7      noPin           

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#define wf_PC8      noPin           

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#define wf_PC9      noPin           

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#define wf_PC10     noPin           

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#define wf_PC11     noPin           

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#define wf_PC12     noPin           

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#define wf_PC13     OUT_2           

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#define wf_PC14     IN              

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#define wf_PC15     IN              

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// ---------------- Port D --------------------

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#define wf_PD0      IN              

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#define wf_PD1      IN              

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#define wf_PD2      noPin           

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#define wf_PD3      noPin           

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#define wf_PD4      noPin           

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#define wf_PD5      noPin           

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#define wf_PD6      noPin           

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#define wf_PD7      noPin           

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#define wf_PD8      noPin           

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#define wf_PD9      noPin           

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#define wf_PD10     noPin           

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#define wf_PD11     noPin           

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#define wf_PD12     noPin           

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#define wf_PD13     noPin           

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#define wf_PD14     noPin           

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#define wf_PD15     noPin           

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/**************** Remap setup ******************/

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#define SPI1_REMAP          0     /* PA4,5,6,7 --> PA15,3,4,5 */

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#define I2C1_REMAP          1     /* PB6,7 --> PB8,9 */

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#define USART1_REMAP        0     /* PA9,10 --> PB6,7 */

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#define USART2_REMAP        0     /* PA0,1,2,3,4 --> PD3,4,5,6,7 */

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#define USART3_REMAP0_3     0     /* 0 = PB10,11,12,13,14  */

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                                  /* 1 = PC10,11,12,PB13,14 */

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                                  /* 2 = not used */

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          /* 3 = PD8,9,10,11,12 */

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#define TIM1_REMAP0_3       3     /* 0 = PA12,8,9,10,11,PB12,13,14,15 */

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                                  /* 1 = PA12,8,9,10,11,6,7,PB0,1 */

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          /* 2 = not used */

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          /* 3 = PE7,9,11,13,14,15,8,10,12 */

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#define TIM2_REMAP0_3       0     /* 0 = PA0,1,2,3 */

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                                  /* 1 = PA15,PB3,PA2,PA3  */

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          /* 2 = PA0,PA1,PB10,PB11 */

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          /* 3 = PA15,PB3,PB10,PB11*/

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#define TIM3_REMAP0_3       0     /* 0 = PA6,7,PB0,1 */

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                                  /* 1 = not used */

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          /* 2 = PB4,5,0,1 */

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          /* 3 = PC6,7,8,9 */

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#define TIM4_REMAP          0     /* PB6,7,8,9 --> PD12,13,14,15 */

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#define CAN1_REMAP0_3       0     /* 0 = PA11,12 */

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                                  /* 1 = not used */

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          /* 2 = PB8,9 */

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          /* 3 = PD0,1 */

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#define PD01_REMAP          1     /* PD0,1 -->  OSC_IN, OSC_OUT */

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#define TIM5CH4_REMAP       0     /* TIM5_CH4: PA3 --> LSI internal Clock */

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#define ADC1_ETRGINJ_REMAP  0     

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#define ADC1_ETRGREG_REMAP  0     

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#define ADC2_ETRGINJ_REMAP  0     

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#define ADC3_ETRGREG_REMAP  0     

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#define SWJ_CFG0_7          0     

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/************* power and clock configuration ***************/

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/* AHB */

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#define en_DMA1     (0<<0)   /* DMA 1 Clock */

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#define en_DMA2     (0<<1)   /* DMA 2 Clock */

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#define en_SRAM     (1<<2)   /* SRAM während Schlafmodus */

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                             /* 3 nix */

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#define en_FLASH    (1<<4)   /* Flash Interface */

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                             /* 5 nix */

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#define en_CRC      (0<<6)   /* CRC-32 (ethernet) Calculator */

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                             /* 7 nix */

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#define en_FSMC     (0<<8)   /* externer Speichercontroller */

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                             /* 9 nix */

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#define en_SDIO     (0<<10)  /* SD-karten-Interface */

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/***** APB1 ************/

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                         /* 31..30 nix */

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#define en1_DAC     0    /* 29 */

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#define en1_PWR     1    /* 28 Power Interface */

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#define en1_BKP     1    /* 27 Backup Interface */

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                         /* 26 nix */

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#define en1_CAN     0    /* 25 */

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                         /* 24 nix */

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#define en1_USB     1    /* 23 */

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#define en1_I2C2    0    /* 22 */

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#define en1_I2C1    0    /* 21 */

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#define en1_UART5   0    /* 20 */

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#define en1_UART4   0    /* 19 konkurriert mit SDIO */

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#define en1_USART3  1    /* 18 */

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#define en1_USART2  1    /* 17 */

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                         /* 16 nix */

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#define en1_SPI3    0    /* 15 */

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#define en1_SPI2    0    /* 14 */

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                         /* 13..12 nix */

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#define en1_WWD     0    /* 11 Watchdog */

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                         /* 10..6 nix */

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#define en1_TIM7    0    /* 5 */

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#define en1_TIM6    0    /* 4 */

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#define en1_TIM5    0    /* 3 */

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#define en1_TIM4    0    /* 2 */

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#define en1_TIM3    0    /* 1 */

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#define en1_TIM2    0    /* 0 */

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/***** APB2 *****/

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                         /* 31..16 nix */

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#define en2_ADC3    0    /* 15 */

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#define en2_USART1  1    /* 14 */

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#define en2_TIM8    0    /* 13 konkurriert mit SDIO */

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#define en2_SPI1    1    /* 12 */

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#define en2_TIM1    0    /* 11 */

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#define en2_ADC2    0    /* 10 */

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#define en2_ADC1    0    /* 9 */

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#define en2_IOPG    0    /* 8 Port G */

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#define en2_IOPF    0    /* 7 Port F */

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#define en2_IOPE    0    /* 6 Port E */

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#define en2_IOPD    1    /* 5 Port D */

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#define en2_IOPC    1    /* 4 Port C */

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#define en2_IOPB    1    /* 3 Port B */

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#define en2_IOPA    1    /* 2 Port A */

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                         /* 1 nix */

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#define en2_AFIO    1    /* 0 Alternative Portbelegungen */

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#define wf_AFIO_MAPR  (SPI1_REMAP)|         \

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                      (I2C1_REMAP<<1)|      \

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          (USART1_REMAP<<2)|    \

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          (USART2_REMAP<<3)|    \

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          (USART3_REMAP0_3<<4)| \

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          (TIM1_REMAP0_3<<6)|   \

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          (TIM2_REMAP0_3<8)|    \

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          (TIM3_REMAP0_3<10)|   \

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          (TIM4_REMAP<<12)|     \

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          (CAN1_REMAP0_3<<13)|  \

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          (PD01_REMAP<<15)|     \

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          (TIM5CH4_REMAP<<16)|  \

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          (ADC1_ETRGINJ_REMAP<<17)| \

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          (ADC1_ETRGREG_REMAP<<18)| \

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          (ADC2_ETRGINJ_REMAP<<19)| \

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                      (ADC3_ETRGREG_REMAP<<20)| \

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          (SWJ_CFG0_7<<24)

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#define wf_GPIOA_CRL  (wf_PA0 | (wf_PA1<<4) | (wf_PA2<<8)  | (wf_PA3<<12)  | (wf_PA4<<16)  | (wf_PA5<<20)  | (wf_PA6<<24)  | (((unsigned)wf_PA7)<<28))

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#define wf_GPIOA_CRH  (wf_PA8 | (wf_PA9<<4) | (wf_PA10<<8) | (wf_PA11<<12) | (wf_PA12<<16) | (wf_PA13<<20) | (wf_PA14<<24) | (((unsigned)wf_PA15)<<28))

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#define wf_GPIOB_CRL  (wf_PB0 | (wf_PB1<<4) | (wf_PB2<<8)  | (wf_PB3<<12)  | (wf_PB4<<16)  | (wf_PB5<<20)  | (wf_PB6<<24)  | (((unsigned)wf_PB7)<<28))

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#define wf_GPIOB_CRH  (wf_PB8 | (wf_PB9<<4) | (wf_PB10<<8) | (wf_PB11<<12) | (wf_PB12<<16) | (wf_PB13<<20) | (wf_PB14<<24) | (((unsigned)wf_PB15)<<28))

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#define wf_GPIOC_CRL  (wf_PC0 | (wf_PC1<<4) | (wf_PC2<<8)  | (wf_PC3<<12)  | (wf_PC4<<16)  | (wf_PC5<<20)  | (wf_PC6<<24)  | (((unsigned)wf_PC7)<<28))

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#define wf_GPIOC_CRH  (wf_PC8 | (wf_PC9<<4) | (wf_PC10<<8) | (wf_PC11<<12) | (wf_PC12<<16) | (wf_PC13<<20) | (wf_PC14<<24) | (((unsigned)wf_PC15)<<28))

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#define wf_GPIOD_CRL  (wf_PD0 | (wf_PD1<<4) | (wf_PD2<<8)  | (wf_PD3<<12)  | (wf_PD4<<16)  | (wf_PD5<<20)  | (wf_PD6<<24)  | (((unsigned)wf_PD7)<<28))

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#define wf_GPIOD_CRH  (wf_PD8 | (wf_PD9<<4) | (wf_PD10<<8) | (wf_PD11<<12) | (wf_PD12<<16) | (wf_PD13<<20) | (wf_PD14<<24) | (((unsigned)wf_PD15)<<28))

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#define wf_AHBENR   (en_SDIO | en_FSMC | en_CRC | en_FLASH | en_SRAM | en_DMA2 | en_DMA1)

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#define wf_APB1ENR  (en1_TIM2<<0)   | \

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                    (en1_TIM3<<1)   | \

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        (en1_TIM4<<2)   | \

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        (en1_TIM5<<3)   | \

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        (en1_TIM6<<4)   | \

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        (en1_TIM7<<5)   | \

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        (en1_WWD<<11)   | \

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        (en1_SPI2<<14)  | \

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        (en1_SPI3<<15)  | \

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        (en1_USART2<<17)| \

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        (en1_USART3<<18)| \

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        (en1_UART4<<19) | \

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        (en1_UART5<<20) | \

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        (en1_I2C1<<21)  | \

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        (en1_I2C2<<22)  | \

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        (en1_USB<<23)   | \

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        (en1_CAN<<25)   | \

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        (en1_BKP<<27)   | \

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        (en1_PWR<<28)   | \

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        (en1_DAC<<29)

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#define wf_APB2ENR  (en2_AFIO)    |  \

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                    (en2_IOPA<<2) |  \

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        (en2_IOPB<<3) |  \

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        (en2_IOPC<<4) |  \

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        (en2_IOPD<<5) |  \

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        (en2_IOPE<<6) |  \

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        (en2_IOPF<<7) |  \

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        (en2_IOPG<<8) |  \

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        (en2_ADC1<<9) |  \

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        (en2_ADC2<<10) | \

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        (en2_TIM1<<11) | \

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        (en2_SPI1<<12) | \

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        (en2_TIM8<<13) | \

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        (en2_USART1<<14) | \

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        (en2_ADC3<<15)

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/* ---------- systick ----------- */

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volatile uint32_t ticks = 0;

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void SysTick_Handler (void)

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{

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  ticks++;

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}

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void systick_init (void)

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{

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  ticks = 0;

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  SYST_RVR = (F_Platform/1000)-1;     

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  SYST_CSR = 7;                       

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}

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void delay_ms (uint32_t ms)

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{

416
  const uint32_t start = ticks;

417
  while(ticks - start < ms);    

418
}

419
420
/* ---------- sysconfig ---------- */

421
422
void sysconfig (void)

423
{

424
  long L;

425
426
  RCC_CIR      = 0;            

427
  RCC_APB1RSTR = 0;            

428
  RCC_APB2RSTR = 0;

429
  FLASH_ACR    = (1<<4) |      

430
    (0<<3) |                   

431
    2;                         

432
433
  RCC_CFGR     = (5<<24);      

434
435
  RCC_AHBENR  = wf_AHBENR;     

436
  RCC_APB1ENR = wf_APB1ENR;    

437
  RCC_APB2ENR = wf_APB2ENR;    

438
439
  GPIOA_BSRR = (1U<<4);        

440
  GPIOA_CRL = wf_GPIOA_CRL;

441
  GPIOA_CRH = wf_GPIOA_CRH;

442
443
  GPIOB_CRL = wf_GPIOB_CRL;

444
  GPIOB_CRH = wf_GPIOB_CRH;

445
446
  GPIOC_CRL = wf_GPIOC_CRL;

447
  GPIOC_CRH = wf_GPIOC_CRH;

448
  

449
  AFIO_MAPR = wf_AFIO_MAPR;

450
451
  RCC_CR    =  (8<<2)|1; 

452
  while ((RCC_CR & 2)==0); 

453
454
  RCC_CR |= (1<<16);      

455
  L = 10000;

456
  while (--L) {

457
    --L;

458
    if (RCC_CR & (1<<17))    

459
      break;

460
  }        

461
462
  if (L) {                       

463
    FLASH_ACR   = (1<<4)|2;      

464
    RCC_CFGR    = (7<<24) |      

465
                  (0<<22) |      

466
                  (7<<18) |      

467
                  (1<<16) |      

468
                  (3<<14) |      

469
                  (4<<11) |      

470
                  (4<<8);        

471
472
    RCC_CR     |= (1<<24);       

473
474
    while ((RCC_CR & (1<<25)) == 0); 

475
    RCC_CFGR = (RCC_CFGR & 0xFFFFFFFC) | 2;

476
    do {

477
      L = RCC_CFGR & (3<<2);

478
    } while (L != (2<<2)); 

479
  }

480
481
  if ((RCC_BDCR & 2)==0) {

482
    PWR_CR |= (1<<8);

483
    RCC_BDCR = (1<<16)|(1<<15)|1;

484
    RCC_BDCR = (1<<15)|(1<<8)|1; 

485
  }

486
}

487
488
/* ---------- main ---------- */

489
490
int main(void)

491
{

492
  systick_init();

493
  

494
  // initialisiere SPI1

495
  SPI1_CR2 = 0x00;

496
  SPI1_CR1 = SPI_CR1_CPHA

497
    | SPI_CR1_CPHA

498
    | SPI_CR1_BR_DIV256

499
    | SPI_CR1_SSM

500
    | SPI_CR1_SPE

501
    | SPI_CR1_SSI

502
    | SPI_CR1_MSTR;

503
504
  // auf SPI1 senden

505
  for(;;) {

506
    // Test ob was kommt -> Signal da auf PA6 ist da!

507
    GPIOA_BSRR = (1u<<6);

508
    delay_ms(1);

509
    GPIOA_BRR = (1u<<6);

510
    delay_ms(10);

511
512
    while ( ! (SPI1_SR & SPI_SR_TXE) );   // wait until TXE = 1

513
    SPI1_DR = 0x33;  

514
    while ( ! (SPI1_SR & SPI_SR_TXE) );   // wait until TXE = 1

515
    while ( (SPI1_SR & SPI_SR_BSY) );     // wait until BSY = 0

516
  }

517
}