tb_AsyncInput.vhd

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-- Engineer: Lothar Miller

--

-- Create Date:   13:43:19 08/13/2008

-- Design Name:   AsyncInput

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_AsyncInput_vhd IS

END tb_AsyncInput_vhd;

ARCHITECTURE behavior OF tb_AsyncInput_vhd IS 

  -- Component Declaration for the Unit Under Test (UUT)

  COMPONENT AsyncInput

  PORT(

    clk : IN std_logic;

    inp : IN std_logic;          

    outp : OUT std_logic

    );

  END COMPONENT;

  --Inputs

  SIGNAL clk :  std_logic := '0';

  SIGNAL inp :  std_logic := '0';

  --Outputs

  SIGNAL outp :  std_logic;

BEGIN

  -- Instantiate the Unit Under Test (UUT)

  uut: AsyncInput PORT MAP(

    clk => clk,

    inp => inp,

    outp => outp

  );

  clk <= not clk after 10 ns;

  tb : PROCESS

  BEGIN

    for I in 0 to 10 loop

      inp <= '0';

      wait for 105 ns;

      inp <= '1';

      wait for 2 ns;

    end loop;

    for I in 0 to 10 loop

      inp <= '0';

      wait for 50 ns;

      inp <= '1';

      wait for 47 ns;

    end loop;

    wait; -- will wait forever

  END PROCESS;

END;