Regcc01.h

/**********************  C51 definitions for T89C51CC01 *******************/

#ifndef _regcc51_h_

#define _regcc51_h_

sfr   P0      = 0x80;

sfr   SP      = 0x81;

sfr   DPL     = 0x82;

sfr   DPH     = 0x83;

sfr16  DPTR   = 0x82;

sfr   PCON    = 0x87;

#define SMOD_   0x80

sfr   TCON    = 0x88;

sbit   IT0     = 0x88;

sbit   IE0     = 0x89;

sbit   IT1     = 0x8A;

sbit   IE1     = 0x8B;

sbit   TR0     = 0x8C;

#define  TR0_  0x10

sbit   TF0     = 0x8D;

#define  TF0_  0x20

sbit   TR1     = 0x8E;

#define TR1_  0x40

sbit   TF1     = 0x8F;

#define  TF1_  0x80

sfr   TMOD    = 0x89;

#define  T0_M0_  1

#define  T0_M1_  2

#define  T0_CT_  4

#define  T0_GA_  8

#define  T1_M0_  0x10

#define T1_M1_  0x20

#define  T1_CT_  0x40

#define  T1_GA_  0x80

sfr   TL0     = 0x8A;

sfr   TL1     = 0x8B;

sfr   TH0     = 0x8C;

sfr   TH1     = 0x8D;

sfr  AUXR  = 0x8E;

#define A0_  0x01

#define EXTRAM_  0x02

#define XRS0_  0x04

#define XRS1_  0x08

#define M0_  0x20

sfr  CKCON  = 0x8F;

#define  X2_  1

#define  T0X2_  2

#define  T1X2_  4

#define  T2X2_  8

#define  SIX2_  0x10

#define PCAX2_  0x20

#define  WDX2_  0x40

#define  CANX2_  0x80

sfr   P1      = 0x90;

sfr   SCON    = 0x98;

sbit   RI      = 0x98;

sbit   TI      = 0x99;

#define TI_  0x02

sbit   RB8     = 0x9A;

sbit   TB8     = 0x9B;

sbit   REN     = 0x9C;

#define REN_   0x10

sbit   SM2     = 0x9D;

#define  SM2_  0x20

sbit   SM1     = 0x9E;

#define  SM1_  0x40

sbit   SM0     = 0x9F;

sbit   FE     = 0x9F;

#define SM0_  0x80

sfr   SBUF    = 0x99;

sfr   CANGIT   = 0x9B;

#define CANGIT_CANIT_    0x80

#define CANGIT_OVRTIM_         0x20

#define CANGIT_OVRBUF_    0x10

#define CANGIT_SERG_    0x08

#define CANGIT_CERG_    0x04

#define CANGIT_FERG_    0x02

#define CANGIT_AERG_    0x01

sfr   CANTEC   = 0x9C;

sfr   CANREC   = 0x9D;

sfr   P2      = 0xA0;

sfr   CANTCON = 0xA1;

sfr   AUXR1     = 0xA2;

#define AUXR1_DPS_  0x01

#define AUXR1_ENBOOT_  0x20

sfr   CANMSG   = 0xA3;

sfr   CANTTCL  = 0xA4;

sfr   CANTTCH = 0xA5;

sfr   WDTRST  = 0xA6;

sfr   WDTPRG  = 0xA7;

sfr   IE      = 0xA8;

sfr   IEN0     = 0xA8;

sbit   EX0     = 0xA8;

#define EX0_   1

sbit   ET0     = 0xA9;

#define ET0_   2

sbit  EX1     = 0xAA;

#define EX1_   4

sbit   ET1     = 0xAB;

#define ET1_   8

sbit   ES      = 0xAC;

#define ES_   0x10

sbit   ET2      = 0xAD;

#define ET2_   0x20

sbit   EPCA    = 0xAE;

#define EPCA_   0x40

sbit   EA      = 0xAF;

#define EA_   0x80

sfr   SADDR  = 0xA9;

sfr   CANGSTA    = 0xAA;

#define CANGSTA_OVFG_  0x40

#define CANGSTA_TBSY_  0x10

#define CANGSTA_RBSY_  0x08

#define CANGSTA_ENFG_  0x04

#define CANGSTA_BOFF_  0x02

#define CANGSTA_ERRP_  0x01

sfr     CANGCON      = 0xAB;

#define CANGCON_ABRQ_    0x80

#define CANGCON_OVRQ_    0x40

#define CANGCON_TTC_    0x20

#define CANGCON_SYNCTTC_  0x10

#define CANGCON_AUTBAUD_  0x08

#define CANGCON_ENA_      0x02

#define CANGCON_GRES_     0x01

sfr   CANTIML  = 0xAC;

sfr   CANTIMH  = 0xAD;

sfr   CANSTMPL= 0xAE;

sfr   CANSTMPH= 0xAF;

sfr   P3      = 0xB0;

sbit   RXD     = 0xB0;

sbit   TXD     = 0xB1;

sbit   INT0    = 0xB2;

sbit   INT1    = 0xB3;

sbit   T0      = 0xB4;

sbit   T1      = 0xB5;

sbit   WR      = 0xB6;

sbit   RD      = 0xB7;

sfr  CANPAGE  = 0xB1;

sfr  CANSTCH  = 0xB2;

#define CANSTCH_DLCW_  0x80

#define CANSTCH_TXOK_  0x40

#define CANSTCH_RXOK_  0x20

#define CANSTCH_BERR_  0x10

#define CANSTCH_SERR_  0x08

#define CANSTCH_CERR_  0x04

#define CANSTCH_FERR_  0x02

#define CANSTCH_AERR_  0x01

sfr  CANCONCH       = 0xB3;

#define CANCONCH_IDE_  0x10

#define CANCONCH_DLC_  0x0F

#define CANCONCH_CONF_ 0xC0

#define DLC_MAX      8

#define CANCONCH_DISABLE_  0x00

#define CANCONCH_TRANSMITTER_  0x40

#define CANCONCH_RECEIVER_  0x80

#define CANCONCH_RECEIVER_BUFFER_  0xC0

sfr  CANBT1    = 0xB4;

#define CAN_PRESCALER_MIN  0

#define CAN_PRESCALER_MAX  63

sfr  CANBT2    = 0xB5;

#define CANBT2_SJW_  0x60

#define CANBT2_PRS_  0x0E

#define CAN_SJW_MIN  0

#define CAN_SJW_MAX  3

#define CAN_PRS_MIN  0

#define CAN_PRS_MAX  7

sfr  CANBT3    = 0xB6;

#define CANBT3_PHS2_ 0x70

#define CANBT3_PHS1_ 0x0E

#define CAN_PHS2_MIN 0

#define CAN_PHS2_MAX 7

#define CAN_PHS1_MIN 0

#define CAN_PHS1_MAX 7

sfr  IPH0  = 0xB7;

sfr   IP      = 0xB8;

sfr     IPL0  = 0xB8;

sbit   PX0     = 0xB8;

sbit   PT0     = 0xB9;

sbit   PX1     = 0xBA;

sbit   PT1     = 0xBB;

sbit   PS      = 0xBC;

sfr  SADEN  = 0xB9;

sfr     CANSIT1 = 0xBA;

sfr     CANSIT2 = 0xBB;

sfr     CANIDT1 = 0xBC;

sfr     CANIDT2 = 0xBD;

sfr     CANIDT3 = 0xBE;

sfr     CANIDT4 = 0xBF;

#define MSK_CANIDT4_RTRTAG 0x04

sfr  P4  = 0xC0;

sbit  TXDC  = 0xC0;

sbit  RXDC  = 0xC1;

sfr  CANGIE    = 0xC1;

#define CANGIE_ENRX_  0x20

#define CANGIE_ENTX_  0x10

#define CANGIE_ENERCH_  0x08

#define CANGIE_ENBUF_   0x04

#define CANGIE_ENERG_   0x02

sfr  CANIE1    = 0xC2;

sfr  CANIE2    = 0xC3;

sfr  CANIDM1    = 0xC4;

sfr  CANIDM2    = 0xC5;

sfr  CANIDM3    = 0xC6;

sfr  CANIDM4    = 0xC7;

#define CANIDM4_RTRMSK_ 0x04

#define CANIDM4_IDEMSK_ 0x01

sfr  T2CON    = 0xC8;

sbit  CP_RL2    = 0xC8;

#define  CP_RL2_    0x01

sbit  C_T2    = 0xC9;

#define  C_T2_    0x02

sbit  TR2    = 0xCA;

#define  TR2_    0x04

sbit  EXEN2    = 0xCB;

#define  EXEN2_    0x08

sbit  TCLK    = 0xCC;

#define  TCLK_    0x10

sbit  RCLK    = 0xCD;

#define  RCLK_    0x20

sbit  EXF2    = 0xCE;

#define  EXF2_    0x40

sbit  TF2    = 0xCF;

#define  TF2_    0x80

sfr  T2MOD  = 0xC9;

sfr  RCAP2L  = 0xCA;

sfr  RCAP2H  = 0xCB;

sfr16  RCAP2W  = 0xCA;

sfr  TL2  = 0xCC;

sfr  TH2  = 0xCD;

sfr16  T2W  = 0xCC;

sfr  CANEN1  = 0xCE;

sfr  CANEN2  = 0xCF;

sfr   PSW     = 0xD0;

sbit  P       = 0xD0;

sbit   F1      = 0xD1;

sbit   OV      = 0xD2;

sbit   RS0     = 0xD3;

sbit   RS1     = 0xD4;

sbit   F0      = 0xD5;

sbit   AC      = 0xD6;

sbit   CY      = 0xD7;

sfr  FCON    = 0xD1;

#define FCON_FBUSY_  0x01

#define FCON_FMOD_  0x06

#define FCON_FPS_  0x08

#define FCON_FPL_  0xF0

sfr  EECON    = 0xD2;

#define EECON_EEBUSY_  0x01

#define EECON_EEE_  0x02

#define EECON_EEPL_  0xF0

sfr     CCON  = 0xD8;

sbit    CF  = 0xDF;

sbit    CR  = 0xDE;

sbit    CCF4  = 0xDC;

sbit    CCF3  = 0xDB;

sbit    CCF2  = 0xDA;

sbit    CCF1  = 0xD9;

sbit    CCF0  = 0xD8;

sfr     CMOD    = 0xD9;

sfr     CCAPM0    = 0xDA;

sfr     CCAPM1    = 0xDB;

sfr     CCAPM2    = 0xDC;

sfr     CCAPM3    = 0xDD;

sfr     CCAPM4    = 0xDE;

sfr  ACC       = 0xE0;

sfr     IEN1    = 0xE8;

sbit    ECAN    = 0xE8;

sbit    EADC    = 0xE9;

sbit    ETIM    = 0xEA;

sfr     CL    = 0xE9;

sfr     CCAP0L    = 0xEA;

sfr     CCAP1L    = 0xEB;

sfr     CCAP2L    = 0xEC;

sfr     CCAP3L    = 0xED;

sfr     CCAP4L    = 0xEE;

sfr  B         = 0xF0;

sfr  ADCLK    = 0xF2;

sfr  ADCON    = 0xF3;

#define ADCON_PSIDLE_  0x40

#define ADCON_ADEN_  0x20

#define ADCON_ADEOC_  0x10

#define ADCON_ADSST_  0x08

#define ADCON_SCH_  0x07

sfr  ADDL    = 0xF4;

#define ADDL_UTILS  0x03

sfr  ADDH    = 0xF5;

sfr  ADCF    = 0xF6;

sfr  IPH1    = 0xF7;

sfr  IPL1    = 0xF8;

sfr     CH    = 0xF9;

sfr     CCAP0H    = 0xFA;

sfr     CCAP1H    = 0xFB;

sfr     CCAP2H    = 0xFC;

sfr     CCAP3H    = 0xFD;

sfr     CCAP4H    = 0xFE;

/****************************** Interrupt sources ***********************/

#define INT_EX0    0

#define INT_T0    1  // Interrupt timer 0

#define INT_EX1    2

#define INT_T1    3

#define INT_UART  4

#define  INT_T2    5

#define  INT_PCA    6

#define  INT_CAN    7

#define  INT_ADC    8

#define  INT_CANT  9

#endif