1 | void timer1_Init(){
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2 | /* TIM1 is on APB2 with clock speed 180MHz */
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3 | /* activate clock for TIM1 peripheral */
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4 | __HAL_RCC_TIM1_CLK_ENABLE();
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5 |
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6 | /* neue Struktur */
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7 | /* Prescaler */
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8 | TIM1->PSC = 35999;
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9 | /* Auto-Reload-Register */
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10 | TIM1->ARR = 19999;
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11 | /* repetition counter if pulse should be displayed more than 1 time */
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12 | TIM1->RCR = 0;
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13 | /* Set the Capture Compare Register: Pulse */
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14 | TIM1->CCR1 = 4999;
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15 | /* Set Clock */
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16 | TIM1->CR1 &= ~ TIM_CR1_CKD;
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17 | TIM1->CR1 |= TIM_CLOCKDIVISION_DIV1;
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18 | /* set counter mode */
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19 | TIM1->CR1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
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20 | TIM1->CR1 |= TIM_COUNTERMODE_UP;
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21 | /* Reset the Output Compare Mode Bits */
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22 | TIM1->CCMR1 &= ~TIM_CCMR1_OC1M;
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23 | TIM1->CCMR1 &= ~TIM_CCMR1_CC1S;
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24 | /* Select the Output Compare (OC) Mode */
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25 | /*
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26 | * Mode 1: In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
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27 | * else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
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28 | * TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
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29 | *
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30 | * Mode 2: In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
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31 | * else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else
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32 | * inactive.
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33 | */
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34 | TIM1->CCMR1 |= TIM_OCMODE_PWM1; //(TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1);
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35 |
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36 | /********** One Pulse Mode Configuration **********/
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37 | /* One Pulse Mode */
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38 | TIM1->CR1 |= TIM_CR1_OPM;
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39 | /********** Slave Mode configuration: Trigger Mode **********/
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40 | TIM1->SMCR &= ~TIM_SMCR_TS;
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41 | TIM1->SMCR |= TIM_TS_ITR1;
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42 | TIM1->SMCR &= ~TIM_SMCR_SMS;
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43 | TIM1->SMCR |= (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1); // = TIM_SLAVEMODE_TRIGGER
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44 | /*************************************************/
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45 | /* Set the Output Compare Preload enable bit for channel 1 */
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46 | TIM1->CCMR1 |= TIM_CCMR1_OC1PE;
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47 | /* update event to reload registers - set the UG Bit to enable UEV */
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48 | TIM1->EGR = TIM_EGR_UG;
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49 | /* Enable the TIM1 Main Output */
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50 | TIM1->BDTR |= TIM_BDTR_MOE;
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51 | /* Reset and set the Output N Polarity level to LOW */
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52 | TIM1->CCER &= ~TIM_CCER_CC1P;
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53 |
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54 | /* Set the Output Compare Polarity */
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55 | TIM1->CCER |= TIM_OCPOLARITY_LOW; //TIM_CCER_CC1P;
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56 | /* Enable the Capture compare channel 1 on High Level*/
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57 | TIM1->CCER |= TIM_CCER_CC1E;
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58 |
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59 | /* Initialization of GPIO_PIN_8 for PWM output */
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60 | GPIO_InitTypeDef GPIO_InitStruct = {0};
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61 | __HAL_RCC_GPIOA_CLK_ENABLE();
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62 | GPIO_InitStruct.Pin = GPIO_PIN_8;
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63 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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64 | GPIO_InitStruct.Pull = GPIO_PULLUP;
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65 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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66 | GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
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67 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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68 |
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69 | }
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70 |
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71 | void timer2_Init(){
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72 | /* TIM2 is on APB1 with clock speed 90MHz */
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73 | /* activate clock for TIM2 peripheral */
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74 | __HAL_RCC_TIM2_CLK_ENABLE();
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75 | /* Prescaler */
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76 | TIM2->PSC = 44999; //44999; /* Oszillator might have problems. Prescaler of 44999 should get at period of 0,0005 but doesn't */
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77 | /* set counter mode */
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78 | TIM2->CR1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
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79 | TIM2->CR1 |= TIM_COUNTERMODE_UP;
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80 | /* Auto-Reload Register */
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81 | TIM2->ARR = 19999; //19999;
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82 | /* Set Clock Division */
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83 | TIM2->CR1 &= ~ TIM_CR1_CKD;
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84 | TIM2->CR1 |= TIM_CLOCKDIVISION_DIV1;
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85 |
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86 | /* Update Event - if this timer is configured as Master with output TRGO_UPDATE
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87 | * the slave timer TIM 1 will get a trigger and run one time
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88 | *
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89 | * This bit can be set by software, it is automatically cleared by hardware.
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90 | * 0: No action
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91 | * 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
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92 | * counter is cleared too (anyway the prescaler ratio is not affected). For more see manual. */
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93 | TIM2->EGR = TIM_EGR_UG;
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94 |
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95 | /* Set Clock Source */
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96 | TIM2->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_TS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
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97 |
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98 | /* Master Configuration */
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99 | TIM2->CR2 &= ~TIM_CR2_MMS;
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100 | TIM2->CR2 |= TIM_TRGO_UPDATE;
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101 |
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102 |
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103 | /* Enable Counter: */
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104 | TIM2->CR1 = TIM_CR1_CEN;
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105 |
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106 | }
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