tb_debounce_fsm.vhd

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-- Company: 

-- Engineer:

--

-- Create Date:   06:45:42 01/08/2020

-- Design Name:   

-- Module Name:   C:/Projekte/FPGA/debounce_fsm/tb_debounce_fsm.vhd

-- Project Name:  debounce_fsm

-- Target Device:  

-- Tool versions:  

-- Description:   

-- 

-- VHDL Test Bench Created by ISE for module: debounce_fsm

-- 

-- Dependencies:

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes: 

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test.  Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation 

-- simulation model.

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY tb_debounce_fsm IS

END tb_debounce_fsm;

ARCHITECTURE behavior OF tb_debounce_fsm IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT debounce_fsm

    PORT(

         clk : IN  std_logic;

         rst : IN  std_logic;

         taster : IN  std_logic;

         debounced : OUT  std_logic

        );

    END COMPONENT;

   --Inputs

   signal clk : std_logic := '0';

   signal rst : std_logic := '1';

   signal taster : std_logic := '0';

   --Outputs

   signal debounced : std_logic;

   -- Clock period definitions

   constant clk_period : time := 10 ns;

BEGIN

  -- Instantiate the Unit Under Test (UUT)

   uut: debounce_fsm PORT MAP (

          clk => clk,

          rst => rst,

          taster => taster,

          debounced => debounced

        );

  clk <= not clk after clk_period/2;

   stim_proc: process

   begin    

      -- hold reset state for 100 ns.

      wait for 100 ns;  

      rst <= '0';

      wait for clk_period*25;

      taster <= '1';

      wait for clk_period*80;

      taster <= '0';

      wait for clk_period*105;

      taster <= '1';

      wait for clk_period*15;

      taster <= '0';

      wait for clk_period*50;

      taster <= '1';

      wait for clk_period*3;

      taster <= '0';

      wait for clk_period*105;

      taster <= '1';

      wait for clk_period*80;

      taster <= '0';

      wait for clk_period*105;

      wait for clk_period*105;

      taster <= '1';

      wait for clk_period*3;

      taster <= '0';

      wait for clk_period*10;

      taster <= '1';

      wait for clk_period*30;

      taster <= '0';

      wait for clk_period*105;

      taster <= '1';

      wait for clk_period*3;

      taster <= '0';

      wait for clk_period*10;

      taster <= '1';

      wait for clk_period*30;

      taster <= '0';

      wait for clk_period*122;

      taster <= '1';

      wait for clk_period*3;

      taster <= '0';

      wait for clk_period*10;

      taster <= '1';

      wait for clk_period*35;

      taster <= '0';

      wait for clk_period*105;

      wait for clk_period*105;

      taster <= '1';

      wait for clk_period*3;

      taster <= '0';

      wait for clk_period*5;

      taster <= '1';

      wait for clk_period*5;

      taster <= '0';

      wait for clk_period*5;

      taster <= '1';

      wait for clk_period*105;

      taster <= '0';

      wait for clk_period*150;

      taster <= '1';

      wait for clk_period*5;

      taster <= '0';

      wait for clk_period*38;

      taster <= '1';

      wait for clk_period*5;

      taster <= '0';

      wait for clk_period*39;

      taster <= '1';

      wait for clk_period*5;

      taster <= '0';

      wait for clk_period*40;

      taster <= '1';

      wait for clk_period*5;

      taster <= '0';

      wait for clk_period*41;

      taster <= '1';

      wait for clk_period*5;

      taster <= '0';

      wait for clk_period*42;

      taster <= '1';

      wait for clk_period*5;

      taster <= '0';

      wait for clk_period*43;

      taster <= '1';

      wait for clk_period*5;

      taster <= '0';

      wait for clk_period*5;

      taster <= '1';

      wait for clk_period*105;

      taster <= '0';

      wait for clk_period*15;

      -- insert stimulus here 

      wait;

   end process;

END;