1 | library IEEE;
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2 | use IEEE.std_logic_1164.all;
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3 | use IEEE.numeric_std.all;
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4 |
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5 | entity debounce_fsm is
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6 | generic( bitdepth : natural := 22);
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7 | port( clk, rst, taster : in std_logic;
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8 | debounced : out std_logic);
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9 | end entity debounce_fsm;
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10 |
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11 | architecture behavorial of debounce_fsm is
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12 |
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13 | type state is (IDLE, WAITING);
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14 | signal current_state : state;
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15 |
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16 | signal counting, endCount : std_logic;
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17 |
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18 | signal countval : unsigned (bitdepth-1 downto 0);
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19 |
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20 | signal MAX_CNT : unsigned (bitdepth-1 downto 0) := to_unsigned(40, bitdepth);
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21 |
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22 | begin
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23 |
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24 | counter : process (clk, rst)
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25 | begin
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26 | if rst = '0' then
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27 | countval <= to_unsigned(0, bitdepth);
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28 | endCount <= '0';
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29 | elsif rising_edge(clk) then
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30 | if countval = MAX_CNT then
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31 | countval <= to_unsigned(0, bitdepth);
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32 | endCount <= '1';
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33 | else
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34 | endCount <= '0';
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35 | if counting = '1' then
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36 | countval <= countval + 1;
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37 | end if;
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38 | end if;
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39 | end if;
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40 | end process counter;
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41 |
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42 |
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43 | transfer_function : process (clk, rst)
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44 | begin
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45 | if rst = '0' then
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46 | current_state <= IDLE;
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47 | elsif rising_edge(clk) then
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48 | case current_state is
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49 | when IDLE =>
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50 | if taster = '0' then
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51 | current_state <= WAITING;
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52 | else
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53 | current_state <= IDLE;
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54 | end if;
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55 | when WAITING =>
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56 | if endCount = '1' then
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57 | if taster = '1' then
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58 | current_state <= IDLE;
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59 | else
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60 | current_state <= WAITING;
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61 | end if;
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62 | end if;
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63 | end case;
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64 | end if;
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65 | end process transfer_function;
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66 |
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67 |
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68 | output_function : process (current_state)
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69 | begin
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70 | case current_state is
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71 | when IDLE =>
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72 | counting <= '0';
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73 | debounced <= '1';
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74 | when WAITING =>
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75 | counting <= '1';
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76 | debounced <= '0';
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77 | end case;
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78 | end process output_function;
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79 |
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80 | end behavorial;
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