debounce_fsm_orig_integer.vhd


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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity debounce_fsm is
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    generic(    MAX_CNT : integer := 40);
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    port(   clk, rst, taster : in std_logic;
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            debounced : out std_logic);
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end entity debounce_fsm;
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architecture behavorial of debounce_fsm is
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    type state is (IDLE, WAITING);
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    signal current_state : state := IDLE;
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    signal counting, endCount : std_logic := '0';
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    signal countval : integer range 0 to MAX_CNT := 0;
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begin
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    counter : process (clk)
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    begin
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        if rising_edge(clk) then
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            if countval = MAX_CNT then
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                countval <= 0;
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                endCount <= '1';
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            else
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                endCount <= '0';
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                if counting = '1' then
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                    countval <= countval + 1;
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                end if;
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            end if;
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        end if;
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    end process counter;
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    transfer_function : process (clk)
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    begin
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        if rising_edge(clk) then
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            case current_state is
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                when IDLE =>
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                    if taster = '0' then
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                        current_state <= WAITING;
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                    else
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                        current_state <= IDLE;
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                    end if;
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                when WAITING =>
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                    if endCount = '1' then
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                        if taster = '1' then
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                            current_state <= IDLE;
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                        else
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                            current_state <= WAITING;
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                        end if;
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                    end if;
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            end case;
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        end if;
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    end process transfer_function;
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    output_function : process (current_state)
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    begin
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        case current_state is
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            when IDLE =>
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                counting <= '0';
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                debounced <= '1';
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            when WAITING =>
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                counting <= '1';
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                debounced <= '0';
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        end case;
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    end process output_function;
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end behavorial;